SN65LVDS311 – about CPOL pin

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Guru 21045 points

Other Parts Discussed in Thread: SN65LVDS311

There are "CPOL=Low" and a description to the data sheet.

(detasheet P13 Figure6)

But, there is no CPOL pin in SN65LVDS311.

Is this description an error in writing?

May I ignore this description?

over 12 years ago

0 Hide over 12 years ago

Guru 21045 points

I have one more questions.

Is input clock polarity of SN65LVDS311 "rising edge"?

0 Elias Villegas M. over 12 years ago in reply to Hide

TI__Guru* 76130 points

Hello,

Yes, data is latched at rising input clock edge, we are still investigating about the "CPOL" question.

Regards.

0 RE over 12 years ago in reply to Hide

TI__Mastermind 20985 points

Kanemaru-san, thanks for pointing this out. Some sections of the LVDS311 have a typo by describing pin CPOL. This pin doesn't exist...it exists in the LVDS301 (80-pin package) and was removed for the LVDS311 (49-pin package) for the tiny 2.8x2.8mm size. Sorry for the confusion and we will update the datasheet. As Elias said, parallel data is latched on the rising edge of PCLK.

Best regards,
RE

0 Hide over 12 years ago in reply to RE

Guru 21045 points

Thank you for answer.

Ｉ understood. thank you very much.

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SN65LVDS311 – about CPOL pin