transmit enable time of SN65HVD33 vs. bus termination

Aseol

Other Parts Discussed in Thread: SN65HVD33

during verification of our design, we’ve found out, that the transmission ready time for SN65HVD33 is bus termination dependent. If the bus is terminated by two 120R resistors on each end, the input state is several ns later on the RS output. If our bus is additional biased with an 10k resistor to vcc and another 10k to gnd, the output stage needs more than 400ns to be ready.

2x120R

2x120R and 2x10k (to vcc/gnd)

Hint: Channel 2 description is wrong, the measure shows RS- line.

does anyone have an explanation for this behavior?

over 12 years ago

0 Jason Blackman over 12 years ago

TI__Genius 14015 points

Hello,

We're going to look into this on the bench and try to figure it out. Stay tuned.

Thanks,
Jason Blackman

0 Aseol over 12 years ago in reply to Jason Blackman

Prodigy 50 points

Hi,

Thanks for getting a closer look to my topic. Maybe it could be helpful to know my setup. I’ve build up a SUT with four participants, each build up as shown below.

Resistor R110 is only mounted on first and last Participant, R112 and R115 are only fitted on first position during second measurement. DE and /RE are connected together to prevent stand by mode.

Cheers

0 Thomas Kugelstadt over 12 years ago in reply to Aseol

TI__Mastermind 28265 points

Aseol,

please connect a 1k to 10 k pull-up resistor between the 3.3Vdd and the receiver output (pin-2) and repeat your measurements.

Thanks, Thomas

0 Aseol over 12 years ago in reply to Thomas Kugelstadt

Prodigy 50 points

Hi Thomas,

Thanks for this hint. On this position was already a 100k built in. We’ve changed the weak resistor to 10k/1k respectively with no mayor effect to the ramp up time. It stayed @402ns with the bus resistor 2x10k and 2x120R.

Aseol

0 Jason Blackman over 12 years ago in reply to Aseol

TI__Genius 14015 points

Hi Aseol,

I was unable to replicate this issue in the lab so far. We have seen an issue before where if the bus common-mode voltage is a diode drop above Vcc, the enable time is significantly longer than normal. Could this be the issue in your case?

Thanks,
Jason

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transmit enable time of SN65HVD33 vs. bus termination