Hi,
We are going to use the TLK10002. At low speed side all four channels of A will be used. They will be connected to an Altera Cyclone IV GX. I am designing the FPGA. The issue is the Lane Alignment Scheme of TLK 10002 is pretty special for me. Is there any Verilog HDL testbench file for that function so as to test my FPGA design? Or is there any Xilinx FPGA reference design on TLK10002 EVB daughter board? Thanks.
Yaoting
ARC
