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FMC daughter card based on TUSB1310A USB3.0 PHY - IO level Mismatch

Sivakumar NM
Prodigy 10 points
Other Parts Discussed in Thread: TUSB1310A, TUSB1310

We are designing FMC daughter card based on TI USB3.0 PHY chip TUSB1310A. This card we targeted for Virtex-6 FPGA Board which usually provides 2.5V IO logic levels on its FMC connectors.

Whereas TUSB1310A PIPE & ULPI signals operates at 1.8V LVCMOS. Is there any way to avoid this IO voltage level conflict? Please suggest.

We felt adding 2.5V to 1.8V level translators on superspeed IO is not advisable and will creates timing issues and signal integrity problems. so please advise the possible way to handle this situation 

  • 0
    TI__Genius 11280 points

    Hello,

    We are reviewing the information y we will contact you soon.

    Regards,

    Gerardo

  • 0
    TI__Genius 11280 points

    Hello Sivakumar,

    The TUSB1310 must be connected directly to the Link Controller (FPGA). In this particular case where FMC daughter card provides only 2.5V IO logic levels, you could use a CPLD to translate between different voltage levels. Typically, the VCCio rail of the CPLD is split, enabling I/O in different banks to be powered at different voltage level. Those CPLD must be as fast as 4ns pin-to-pin delay to achieve a 250 MHz interface. Note this is only a suggestion and it hasn't been implemented by TI.

    Regards,

    Gerardo