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SN65LVDS100 - Single-Ended CMOS-to-LVDS Translation

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Guru 21045 points
Other Parts Discussed in Thread: SN65LVDS100

My customer uses a circuit of Figure42(VDD=1.8V*) of datasheet P15 .

(VDD=1.8V is My customer's Condition.)

 

Will the threshold of CMOS input be as follows?

・VIT+ = 0.9V + 0.1V = 1.0V

・VIT- = 0.9V – 0.1V = 0.8V

* 0.9V is 3pin Voltage.

(VDD/2 = 1.8V/2 = 0.9V)

 

In the case of the above,

"CMOS input (2pin) = 0.375V" is recognized to be Low Level.

"CMOS input (2pin) = 1.125V" is recognized to be High Level.

Is my understanding of this correct?

  • 0
    TI__Genius 13475 points

    Yes, this is correct.   The input to the SN65LVDS100 is a differential input, in the circuit in Fig 42 one side of that input is being biased at a DC level, set by the combination of Vdd and the ratio of the two resistors.   The input voltage threshold for the 'LVDS100 is 100mV, so setting the bias anywhere between about 500mV and 1000mV will result in operation.

    If the bias point is not at the mid-scale point betwen Vol and Voh, it is possible that you will see some duty cycle distortion.   Depending upon the coding of the signal,  you may be able to derive the bias from the input signal itself by connecting a capacitor from the inverting input to GND, and a large resistor between the CMOS output and the inverting input - this will drive the non inverting input with a bias point which is near the average of the input signal.