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TUSB1310A Based Daughter Card Schematics Review

Other Parts Discussed in Thread: TUSB1310, TPS2560

Hi ,

Please find the attached file as a schematic we are designing for our IP developnment and we want our design will be validated by TI.

Please review it and revert for necessary updation to be done in this .

We are designing Xilinx-Vertex 6 based FPGA , USB 3.0 validation platform and wants your suitable suggestion from your side.

Its a nice pleasure if i heard a early reply from your side.

Thanks

Vikas Gupta

  • Hello,

        I just Reviewed the schematic and I have the following notations and suggestions about it:

    • Please ensure You have a 90.9-k 1% resistor from the cable VBUS connector to the USB VBUS terminal on the TUSB1310 and a 10-k 1% resistor from USB VBUS to ground
    • If the design is Bus Powered, use of the TI TPS2560/61 is recommended. Inrush current can occur on VBUS when a function is plugged into the network.
    • The high-speed differential pair (USB_DM and USB_DP) is connected to a USB type B connecter. The diff pair traces should be routed with 90-Ω ±15% differential impedance. The high-speed signal pair should be trace length matched. Max trace length mismatch between High speed USB signal pairs should be no greater than 150 mils. Likewise ESD clamps should also be placed as close as possible to the USB connector signal pins (closer than the choke).
    • Each SuperSpeed diff pair traces should be routed with 90-Ω ±15% differential impedance. The high-speed signal pair should be trace length matched. Max trace length mismatch between SuperSpeed USB signal pairs should be no greater than 2.5 mils. The transmit diff pair does not have to be the same length as the receive diff pair. Keep total trace length to a minimum. The transmitter diff pair requires 0.1-µF coupling caps for proper operation. The package/case size of these caps should be no bigger than 0402. C-packs are not allowed. The caps should be placed symmetrically as close as possible to the USB connector signal pins. If a common mode choke is required then place the choke as close as possible to the USB connector signal pins (closer than the transmitter caps). Likewise ESD clamps should also be placed as close as possible to the USB connector signal pins (closer than the choke and transmitter caps). It is permissible to swap the plus and minus on either or both of the SuperSpeed differential pairs. This may be necessary to prevent the differential traces from crossing over one another. However it is not permissible to swap the transmitter diff pair with the receive diff pair.
    • The ULPI signals are 1.8-V LVCMOS. They should be as short as possible and matched in length, with a single ended impedance of 50 Ω ±10%.
    • Parallel data: External source series termination resistors are not required if the interface is kept to less than two inches in length with an impedance of 50 Ω ±10%. Routing this interface longer than two inches or through a connector is not recommended. If this must be done, special care must be taken to select the proper high-speed connector as well as modeling of the transmission line. Post route modeling of the circuit is recommended.

    Best Regards,

    Diego.

  • Thanks Diego, i also wat to know that this design is well good connectivity wise , pin outs & ins and resistor values. if any thing from that side , suggeation will be welcome.

    thanks

    Vikas

  • Hello Vikas

        Unfortunately We don't have an EVM for the TUSB1310 and each customer has it's own implementations. However I can provide You the official implementation guide, were You can find the guidelines listed below and even more information.

    TUSB1310 implementation guide:

    http://www.ti.com/lit/an/sllu123/sllu123.pdf

    PD: feel free to send any of your questions/issues about the implementation

    Best Regards

    Diego.