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SN65LV1023A TCLK Jitter

wolfgang kopp
Intellectual 450 points
Other Parts Discussed in Thread: SN65LV1224B, SN65LV1023A

We use the SN65LV1023A LVDS transmitters with 30Mhz TCLK and the SN65LV1224B receiver looses the lock from time to time.

At the moment we think a jitter on TCLK is responsible for that.

But we do not see a RMS jitter greater 150ps on the transmitter side.

Is there another jitter restriction (pk-pk) on the serializer?

Best regards,

Wolfgang

  • 0
    TI__Mastermind 20820 points

    Hi Wolfgang,

    Not that I am aware of, try sending a re-synch pattern every so often to realign the de-serializer PLL with the serializer. If these they drift apart over time this may cause you to loss lock. 

    Regards,

    Mike

  • 0 in reply to Michael Peffers
    Intellectual 450 points

    Dear Michael,

    I am thinking that the PLL syncs with the embedded START-STOP bits. Once locked the LVDS should run for days without the need to re-synch with the special sync patterns.

    If we improve TCLK jitter to about 30ps RMS the LOCK is ok.

    With a bad setup of 80ps RMS jitter we randomly lose the lock. We never reached 150ps RMS, which should be the limit according to the datasheet.

    We believe we have a problem with the PEAK jitter or cycle-to-cyle jitter here, but there is no limit datasheet.

    Best regards,

    Wolfgang

  • 0 in reply to wolfgang kopp
    TI__Mastermind 20820 points

    Hi Wolfgang,

    Can you look at the amount of jitter on the input signal to the SN65LV1224B? The fact that the device remains locked if you lower your refclk jitter tells me that you have some high frequency jitter on your data. The CDR may have trouble tracking the dat while it is sampling if that jitter becomes to great and crosses the threshold, which could cause you to lose lock.

    Regards,

    Mike

  • 0 in reply to Michael Peffers
    Intellectual 450 points

    Dear Mike,

    we looked at the REFCLK on the receiver already but it looked fine. We made improvements of the jitter on the TCLK of the transmitter and the lost lock disappeared. Also the LVDS data eye pattern looks fine. Is it possible to disturb the transmitter with jitter on TCLK that the data is corrupted and a does not send a START/STOP bit?

    Best regards,

    Wolfgang