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SN65LVDT2 MAX ESD PROTECTION DIODE CLAMPING CURRENT

WhiteHorse
Genius 4430 points
Other Parts Discussed in Thread: SN65LVDT2

Customer needs to know what the maximum clampig current is for par number SN65LVDT2.

Thanks for your help.

John

  • 0
    TI__Genius 14317 points

    John,

    Can you be more specific? With respect to the ESD ratings and peak currents, which pins?

  • 0 in reply to Jeffery Pfarr
    TI__Genius 14317 points

    OK, some time has passed with no response so, I'm going to speculate that you mean the bus pins (In and Out). The Data Sheet spec for bus pin HBM ESD is 9 kV when tested per JEDEC Standard 22, Test Method A114-A. That test method specifies 1500 ohms in series between the ESD source cap and the DUT (Device Under Test). When the bus clamp zener diode to GND is on, it clamps at 7 V and the on resistance is only a fraction of the 1500 ohm series resistance (<100 ohms or so). Therefore Ip is approximately equal to  9 kV/1600 ohms = 5.625 A and follows a duration and profile that is defined in the JEDEC Test Method spec. This applies for input or output +9 kV ESD testing and for -9 kV ESD testing.

  • 0 in reply to Jeffery Pfarr
    Genius 4430 points

    Sorry for the delay in my response Jeff.  For some reason I don't always receive an email when a post has be replied to.  I believe your response will answer the customer's question.  Their concern was they had a pull up resistor tied to an output of the SN65LVDT2.  The pull up resistor was connected to a 5V supply and the customer wanted to ensure that the current that the pull up resistor introduced would not stress the ESD diodes on the SN65LVD2.  I explained that the pull up would have to over drive the output stage before the ESD diodes would be affected.  We finally setteled on proving the max clamp current (for the I/Os) and they would be content.

    Regards,

    John