This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65HVD10 single-ended input rise time requirement

Other Parts Discussed in Thread: SN65HVD10, SN74LVC2G14

The SN65HVD10 does not spec the input signal rise time requirement or a dv/dt for the single-ended signal D (pin 4) of the part.  Per the app note "SCBA004C - Implications of Slow or Floating CMOS inputs", I'm assuming there are issues with slow rise times on this pin, but is there any guidance anywhere per what the limitations are?  The application I'm looking at could have a very slow rise time, in the 100's of nanoseconds, to low digit microseconds.  It would be monotonic, shouldn't be noisy,... but slow.  I'd like to know if I'm going to run in to reliability issues if I don't schmidt trigger this input.

 

Thanks,

Mark 

  • Mark,

    first, why are you using a high-sped (32Mbps device) when a 1Mbps would do for slow signals i.e. HVD12 (1Mbps) or HVD72 (250kbps)?

    with the fast HVD10 you could have data errors when not schmitt-triggering the D input.

    regards, Thomas

  • Thomas,

    Thanks for the quick reply.   The "slow" interface is the DS1821 open-drain/bi-directional/single-wire temperature sensor interface.  The ultimate place for the data is an FPGA, so everything else in the link is going to have rise/fall time requirements.  I was hoping there was some hidden/non-advertised hysteresis in the single-ended side of the HVD10 that would allow me to use it without another device in front of it (since there was no information at all about the single-ended input on the datasheet).  Otherwise, I'll need 2 devices in front of it to schmitt trigger the input as well as implement the outgoing side as well. But your response sort of hints that there is no such luck with the hvd10 and I do in fact need to place the schmitt trigger stage in front.  Out of curiosity though, would the hvd10 inputs be similar to the LV specs in the appnote I referenced?

     

    Thanks,

    Mark

  • Marc, the input of the HVD10 is not like the LV inputs described in the mentioned app-note. On page 12 of the HVD10 data sheet, top left corner, you see an equivalent input diagram of the D-input. It has an internal 100k pull-up, so it is not floating. I usually adding an external 4.7k or even 10k pull-up for stronger biasing in noise environment as the internal 100k only provides weak biasing and can be easily overwritten by small noise signals. Add some slow input signal to it and you could have some noise "chatter" when crossing some internal threshold.

    Here is what I'm thinking how you could tackle the slow signal issue: Since the DQ pin of the DS1821 is open collector, use the 4.7k pull-up as shown in the "Hardware configuration" of the DS8121 data sheet, apply a dual inverting schmitt-trigger buffer, SN74LVC2G14, and connect its output to the D-input. You can still apply a 4.7k pull-down to the D-input too, simply to ive this input a defined voltage level during power-up.

    I always add a few pull-down resistors to the logic I/Os of anRS-485 transceiver to give it a defined state during power-up.

    I hope this helps a bit.

    Best regards, Thomas

  • I should also add that I had some incentive to just use the hvd10, I work at a large corporation and that part's been used before, is in our design library, on our standard parts list, and doesn't need a 2 week review/processing to get it in to our design (which is behind schedule).  If I did happen to go with the hvd72, could I do it without the schmitt trigger?

  • I'm afraid, not, as none of our RS-485 transceiver has schmitt-trigger inputs.