Ethercat, TLK110 and "frame lost" - RX_ERR issue

I believe that the receive errors are being caused by poor signal integrity of the receive signals.  The key will be to determine the cause of the poor signal integrity.  I understand that your design is broadly cut and paste from the ICE board, but could you provide a schematic for review?  That would be the best starting point.

As a point of reference, below is an oscilloscope shot of scrambled idles taken on one of our EVMs. 

It is transmit signaling rather than receive signaling so it is not a 1-to-1 comparison, but it should provide you with an idea of what I would consider high quality signal integrity.  The goal for your board should be to clean up the ringing and overshoot in the signals to look more like this scope shot.

Patrick

In attached pdf file you can see the Ethercat PHY schematic of our board:

5861.6712.ethercat.pdf

In our board TX signals are very close to the ones you posted. RX ones are not so nice...

We followed all the "best practice" rules for routing fast signals (impedance matching, etc...), with no result.

I've tried to:

- shorten up distance between magnetic and phy (less than 5mm) with no result at all.

- use 100 ohm and then 25 ohm terminating resistors (instead of 50ohm), with no result. Same error rate; I had expected a poorer signal quality and a greater error rate.

- apply 100pf (!) capacitor in parallel to terminating resistors. Same as previuos: poorer signal, same performances.

In conclusion: signals between magnetic and phy seems very robust: I cant' get them worse than they actually are.

Problem is: how can I make them better?

Please note that the ethercat master that is generating ethercat signals works fine with ICE demoboard, with no error at all. The issue is not related to the master of the bus.

Thank you for your reply. This is the situation, so far:

1. R6310: removed. No change in signal and same error rate.
2. In ICE demoboard is 4.99K (R159, AM335X_15X15_ICE.dsn sheet 9/14). Is RBIAS value critical? 
3. still testing (pre-production board is temporary back to our supplier)
4. 49R9 value change (and parallel capacitor) was a "desperate try". I've switched back to right values after a quick glance to the signal (NOTE: those value did not affected error rate).
5. I've tried several link partners and very short cables (less than 20cm): no better, no worse.

Hi Eugenio,

lets try the following:

1. i observe in the pdf that there are 2 sites of tlk110, the 1st device is d70 and the 2nd is d72. why is only the 1st device connected to magnetics? what happens with the 2nd device, is it connected to another  magnetic which is not in this PDF?
2. what device gives the errors, is it D70 or D72?
3. can you send us register dump from both sites strating from address 0x0 till 0x1f
4. when you observe the RX_error does the link fail afterwards (or is it still a stable link)?
5. what size of packets are you transferring? can you tell what is the packet length and IPG (inter packet gap)?
6. can you measure with scope the 3.3v on component D118  on pins: CTTX, CTRX look for correct DC voltage. do you see any ripples? can you do the same observations on TLK110 D70, pins: 20,21,22,32,48.
7. can you please check the voltage on the PFBOUT, pin 23. it should show 1.55v +-5%
8. can you verIfy RBIAS voltage is 1.215v +-5%
9. can you please check the xi clock with a scope?
10. can you please read register 0x218 couple of times on those occasions where you observe the RX error

you can contact me directly at: aviad@ti.com

Thanks,

Aviad