About 10 Mb/s Serial Mode Timings

Sorry, the component I talk about is DP83848I. Thank you.

The RX_CLK High/Low Time in 10 Mb/s Serial Mode (Parameter T2.14.1 in the DP83848I datasheet) is a design characteristic related to the clock recovery.  This is indicated in the note below the table.  Dependent on the frequency difference between the received data and the reference clock, the high/low time of the recovered clock may shift.

Patrick

Hello, and thank you for your first answer. The shift of the clock is randomly (function of the frequency difference between the received data and the reference clock) and so RX_CLK High/Low Time can randomly be at 35ns or 65ns(during the life of the component)  is it true ?

No way (measures on the component after manufacturing, measerd at special temperatures...) can guaranty better timings (as 40/60% for exemple) ? My question is because we use a processor component that seems only to accept 40ns RX_CLK high time minimum.

Thank you,

Baptiste.

Baptiste,

That is correct.  There is no way we can guarantee a minimum RX_CLK high timing of 40ns.  The timing is an artifact of the design architecture.

Patrick

And could you propose a TI timing component( a type of duty cycle corrector component) that could fixe the values of those timing to reduce it at 40ns/60ns ?