SN65ELT23 sample schematic

Barani,

I've moved this to the High Speed Interface Forum for you.

Thanks Mike.

The reason we wanted to see the schematic is we got confused about the

· Internal Input 50-kΩ Pull-Down Resistor ?? Is the internal pull down for all PECL diff input. If so, why we need external pull up and pull down?

Also, we are in need of another help. We are using a TI part  DS91C180. But, we need a dual TX and RX with same characteristics.

Found, SN65LVDM050-Q, SN65LVDM051-Q,  and SN64LVDS049  Any suggestion on which one would be a good fit. We have a PECL to TTL @ 125 MHz (clock and data coming that have to converted to LVTTL for FPGA interface).

Thanks

Hi Barani,

Is the internal pull down for all PECL diff input. If so, why we need external pull up and pull down?

Yes, the 50k ohm pull down resistors are on all differential inputs. The external resistor divider assumes AC coupling and is used to set the termination voltage V_TERM and for impedance matching of 50ohms. Here is helpful app note for reference: www.ti.com/lit/an/slla120/slla120.pdf.

Take a look at this app note on MLVDS: http://www.ti.com/lit/an/slla108a/slla108a.pdf. It does a good job in explaining the topic and at the end there is a table listing all of TI's offerings in the MLVDS space. If you have any more questions please feel free to ask.

Regards,

Mike