Hello,
We used XIO2001 in our design. The brige could only be recognized in certain slots. We tried to locate the fault, but failed.
The following are our problems and speculation.
1. The implementation doc says "IDSEL for each PCI bus device must be resistively coupled (100 Ω) to one of the address lines between AD31 and AD16", but we just give a series resistor(100 ohm). Does the "coupled to" means I could give a series resistor for simple or IDSEL and AD* must have a 100 ohm Characteristic impedance like diferential pairs???
2. In some PCI slots which can recognize our bridge, we could detect the 33MHz clock sent by XIO2001. Similarly, we couldn't detect the 33MHz clock in the slots which cannot recoginize our bridge. I want know the 33MHz clock will send out from XIO2001 after the PCIe lane has been successfully trained or only after the 100MHz diferential refClk is stable.**************************
3. The XIO2001's implementation doc syas "Trace length differences over all segments are additive and must be less than 5 mils". In our PCB, the total length diference is less than 5mils, but the length in segments are not well match. For example, in segment A, the diference is +12mil. In seg B, the diference is -7mils. So the total diference is less than 5mils. Does the mismatch in segment could cause error in some slots???
