DS92LX1622
Please allow me clearing the relationship between PDB, LOCK and LVCMOS outputs.
DS92LX1622 LVCMOS output may be set to active, High-Z or Low under the conditions
of PDB, LOCK and register bits in Address 0cx02.
Please let me confirm if the table below truly shows the relationship
PDB LOCK (OSS_sel bit) LVCMOS output
L x x High-Z
H L ‘0’ All L
H L ‘1’ High-Z
H H x Active Data
Likewise, please let me confirm the relationship between PDB, LOCK and Clock output.
PDB LOCK (Auto Clock bit) Clock output
L x x L
H L ‘0’ L
H L ‘1’ 25 MHz internal clock
H H x Recovered clock
Mita
