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Interfacing IEEE1394b with TSB41BA3D

Matthew Greci
Prodigy 60 points
Other Parts Discussed in Thread: TSB41BA3D, TSB81BA3E

Hello,

I am currently working on trying to connect a Raspberry Pi, to the TSB41BA3D physical layer chip. I have a problem with setting this chip up. 

In particular, pin 34, CPS, "Cable-power status input." I do understand that this pin is an input, but I am unsure where the form. It says "cable power," but what does that mean? Does it mean it comes from one of the 9 pins in the firewire port? I do not fully understand this pin.

Any information would be very helpful. Also, I am working on interfacing with IEEE 1394b only. It would be great to hear that there is a newer chip available, but I do not want to interface with PCI/PCI Express. 

I also heard about a new chip, TSB81BA3E. Can someone tell me a little about that chip? Is it physical layer only? Does it not require PCI?

Thank you again.

  • 0
    Guru 317060 points

    The datasheet says:

    This terminal is normally connected to cable power through a 400-kΩ resistor.

    This would be the connector's VG pin.

    But how do intend you connect the CTLx/Dx pins? The Pi's CPU is not fast enough to implement the PHY-link interface with GPIOs.

    You really should use a hardware link implementation.
    If you don't want to use PCI(e), forget about 1394b, and use something like the TSB43EB42 or TSB12LV32.

  • 0 in reply to Clemens Ladisch
    Prodigy 60 points
    Thank you for the very fast reply.
    I am wondering what you mean when you say the Pi is too slow. Its processor runs at 700 MHz and the TSB41BA3D requires at 98 MHz clock. Are you saying that the process of directly controlling the GPIO pins is too slow?
  • 0 in reply to Matthew Greci
    Guru 317060 points

    If all you had to do was to generate a single square wave signal, you might be able to toggle a GPIO every three and a half cycles (although the timing would likely be off).

    However, reading and generating the correct bit pattern on all pins, reading and writing the data from/to memory, and correctly handling the quite complex link state machine is not possible within the timing constraints you have.