We need to simulate the RTL code for the project using the TUSB1310A. For that, we need the PHY model ( Verilog model). Can you help me in getting the model? It is not the IBIS model but the actual Verilog or VHDL model.
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We need to simulate the RTL code for the project using the TUSB1310A. For that, we need the PHY model ( Verilog model). Can you help me in getting the model? It is not the IBIS model but the actual Verilog or VHDL model.