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SN75LVC600S SATA Signal Conditioning Question

Tom Roe1
Prodigy 90 points

I am trying to figure out how the SN75LVC600s works in our system. I searched the Blog for the part number but nothing turns up and understandably the data sheet really doesn't show how the part really functions.

Please take a look at the waveforms below.

 The upper waveform is at the input pins to the 600s and the lower one is the output.

I use a good simulator (Ansoft HFSS and Ansoft Designer) for this channel and it does not show any large impedance miss-matches so this signal path must have some other explanation.  I also have very good power integrity on this board. The buried capacitance is very high and the power signals look great on the high speed scope.

I am wondering if the 600S could be seeing the input as low somehow causing the large rise and then crush in the eye at the output? Any ideas would be great.

We don't have an HSPICE simulator here so I can't actually get an in/out view of the model.

This is a 3 Gbps SATA line and it works great without any bit errors that we have found. The Eye is plenty large enough for our receiver at 3G, but we want to use the 600s for another 6Gbps product and so I want to understand where this type of abnormality could be coming from.

Pictures taken with a Tek 72004, 20GHz scope and P7520, diff 20 GHz probe soldered to the pins of the device with less than a 10th of inch of line. DE and DQ are zero.

Any insight into the functionality of the IC and what could be causing this dip in the output would be great.

Input to SN75LVC600S from the driver on the VPX Backplane:

 

Output from 600s which is into a 100 Ohm diff receiver with very good signal integrity lines according to my simulations DE and EQ are set to zero: 

Thanks

Tom

thomas.roe@elma.com

  • 0
    TI__Guru* 76130 points

    Hello Tom,

    We have received your question and we'll reply soon.

    Regards.

  • 0
    TI__Guru* 76130 points

    Hello,

    Please see below comment from our experts:

    "

    The device's drivers are optimized for 6Gbps operation.  The waveforms they have taken are at 3Gbps, so at 6Gbps the bit period would be half what they have.  The dip occurs where a 6Gbps signal would be transitioning.  So basically the 600S is driving two 6Gbps cycles for every 3Gbps(The dip occurs between driving the 6Gbps bits).  

    "

  • 0 in reply to Elias Villegas M.
    Prodigy 90 points

    Ok thanks.

    So if I were to use this part at 1.5Gbps there would be 2 humps? I don't have a 1.5G set up to check it.  I know the eye is great without bit errors that we can measure, but I just want to understand a little about the inside of the device.  So I guess it is kind of a charge pump. After it receives a logic high/low it pumps out a burst if the logic is still high/low on the next opportunity it puts out another burst?  

    Also is most of the burst frequency content at the 6 Gbps 1st Harmonic (3 GHz) or does it just look that way because of the transmition line filtering?

    Thanks again

    Tom