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DS34RT5110 and high input jitter

PAMELA DE FIORIDO
Prodigy 10 points
Other Parts Discussed in Thread: DS34RT5110

Hi,

I have a problem using the DS34RT5110, I can't see the playback image if the input clock jitter is high.

It seems that when the input clock jitter is high (close to 0.25Tbit), the output clock, generated by the CDR of the DS34RT5110, is continuously phase shifted.

I suppose this could be the same problem exposed in the post "DS34RT5110 having good margin for HDMI tests but no image in playback, Apr 03 2012", I'm using the same  settings (BYPASS = low, EN = high, MODE = low, VOD_CRL = 24kohm to GND (DC coupled)) and having the same results (playback immage appear only if  BYPASS = high or MODE = high).

I think that I don't see the playback image because the monitor connected to the DS34RT5110's output is not able to hook up the clock due to his continous phase shifting, If I connect the signal generator directly to the monitor (without pass through the DS34RT5110) it works, so, in this cases, the use of DS34RT5110 restricts the system operating conditions.

If my suppositions are right, are there some solutions to limit the output clock phase shifting?

For example, changing the loop filter components can I avoid this problem? (and how to do?, where can I find some more detailed informations on how DS34RT5110 operates?)

I'm not expert on these subject, so please tell me if I wrong something.

Many thanks in advance.

  • 0
    TI__Guru* 93670 points

    Hi Pamela,

    I appologize for the long delay to respond to your question above. I just became aware of this post.

    You are correct by changing the loop filter external RC values you are essentially chaning the loop bandwidth and it may have some effect however i think we need to understand this issue a bit more ti enable us to find the root cause.

    You may have already run this test but in a case, could you please run a test where you just change to MODE to HIGH and leave BYPASS = Low. In this case does the monitor recover the video correctly? If this is the case, then as you mentioned the problem is due to the perhaps high jitter on the clock signal. Please let us know.

    Regards,,nasser