• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 561 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83640 CLK_OUT

BALANESCU DAN1
Prodigy 10 points
I have a problem with my custom board based on DP83640TVV (VT25AF).
The strap resistors select RMII Master mode.
I have 50Mhz on RX_CLK and TX_CLK, but on CLK_OUT the frequency is 25Mhz.
As I know, the CLK_OUT output frequency must be equal  with RX_CLK and TX_CLK.
Please help !
  • 0
    TI__Mastermind 31600 points

    Please see section 2.1 of the RMII Master mode application note (http://www.ti.com/litv/pdf/snla101).  I have included the relevant text below:

    In addition, if the CLK_OUT pin is to be used as a 50 MHz RMII clock, the default PTP clock output
    function must be disabled by clearing bit 15 (PTP_CLKOUT_EN) in register 0x14 (PTP_COC).

    Patrick

  • 0 in reply to Patrick OFarrell
    TI__Mastermind 31600 points

    To help with better supporting and tracking your future questions in Ethernet, please post any new Ethernet related questions into the Ethernet Forum. We are working on changing the description of the Industrial Interface forums to better describe what devices are supported.

    Patrick