• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 298 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Synchronization between two TLK2541

Robert Spieler
Prodigy 10 points
Other Parts Discussed in Thread: TLK2501

Hi,

We connected a TLK2541 to a FPGA to transfer 16-bit data via fiber to another board with TLK2541 and FPGA.
During initial tests we found that the byte alignment is not always correct.
This happens during PLL lock and is stable after that.
We use 8-bit/10-bit decoding to have a balanced data stream.

Unfortunately the datasheet is not very clear about that:
On page 14 at the bottom it says: "The first data bit received is output on RXD[0]."
On page 16 is says: "The TLK2541 only achieves byte alignment on the 0011111 comma."

We planned to transmit raw 16-bit values directly from the ACDs.

Do we have to implement a protocol layer in order to align the bytes correct?
Do you have application notes or application samples that help us to implement this quickly?

How can we find out that the TLK2541 has locked onto the data stream?
There are no flags available.

Thanks and regards

Robert

  • 0
    TI__Mastermind 20820 points

    HI Robert,

    Unfortunately you are going to have to find a way to generate the comma pattern (K28.5) on the parallel side prior to sending the data from the ADCs to the TLK2541. The TLK2541 uses this sequence of bits as an alignment character. I do not know of any application reports that describe a quick way to implement such a thing external to the SerDes but I am sure it can be done with careful planning.

    TI does offer the TLK2501 which is a SerDes device that has the capability self generating its alignment character by toggling a couple of pins on the device.

    Regards,

    Mike

  • 0 in reply to Michael Peffers
    Prodigy 10 points

    Hi Mike,

    Thank you for the fast response.

    Generating the comma pattern is not too difficult as the ADC samples run through the FPGA first before they hit the SerDes.
    I believe this has to be done regularly in case the stream is interrupted or the receiving side (the PLL) looses sync.
    Or we implement a kind of handshake using the return path to inform the sender about PLL-sync loss or PLL re-sync.

    This was another question in my previous post:
    How can the SerDes inform the FPGA that its PLL lost sync and had to re-sync?

    Regards

    Robert