Hi, for evaluation I am using the SDALTEVK HSMC SDI ADAPTER BOARD together with a Cyclone 3 Evalboard. In my final application, I want to transmit using a 72 MHz Tx-clock (720 MHz SDI rate), which should be well within the LMH0340 specification. However, The device does only go into PLL-lock below 33 MHz and within the 124 to 168 MHz Tx-clock range (did not test higher rates above 200 MHz). The data applied is a "1010.." test pattern, however the pattern used seems to have no influence. Timing is verified with a 40 GS (6 GHz bandwidth) scope.
The loop filter is first left on standard values (100nF / 500 Ohm) as populated on SDALTEVK, however, even change of components did not influence lock frequency range.
Do you have any hints on locking to a 72 MHz Txclock range? My current assumption is, that the LM0340 actually has three internal VCOs (PLLs), one for SD-, HD- and 3G-SDI rates and thus may not operate in non-standard frequencies in between.
I can switch my system design to use a 144 MHz rate, which does work, however I only needed 720 MHz and wanted to use the lower cable attenuation for the lower bandwidth. But if that does not work and I am not just doing something else wrong, I just may use the 144 MHz rate.
Best Regards
Henning
