Hello,
I am using the DP83640 and I am trying to apply AN-1729 to align the CLK_OUT phase, but it has no effect on the clock phase.
I am monitoring the reference clock (on X1) and the CLK_OUT and I tried to write different correction values in the PTP_TDR register to do a step adjustment to the 1588 clock time:
• Write the correction value to PTP_TDR. (Correction = 2 * ref_period + avg_phase_error)
• Write PTP_STEP_CLK (0x8) to PTP_CTL.
But I see no change on the CLK_OUT phase with respect to reference clock.
1- Am I doing something wrong?
2- Is the PTP_TDR value unit in nano seconds or in reference clock period (8ns)?
Thanks in advance for your help
Eric
