The serializer is specified from 125MHz to 312.5MHz (1.25Gbps to 3.125Gbps).
I want to ensure the following observations are correct
Since it is a LVDS DDR interface, without using DC balancing, the 5-bit inputs are used to create 10-bit words which are then serialized.
Therefore 125MHz x 10-bits = 1.25Gbps, and 312.5MHz x 10-bits = 3.125Gbps
In referencing Table 4 of the datasheet, it specifies a minimum latency of 10-11 clocks + 5.5 ns. But the "clocks" are specified at 1/2 clockIN rate
Therefore for 1.25Gbps, the minimum latency is (1/62.5MHz x 10 clocks + 5.5ns) --> 16ns x 10 + 5.5ns = 165.5ns
For 3.125 Gbps, the min latency is (1/156.25MHz x 10 clocks + 5.5ns) --> 6.4ns x 10 + 5.5ns = 69.5ns
However, in the case where DC balancing, scrambling, etc, is used the max data payload achievable is 2.5Gbps
Since a 20-bit word is created, this implies that the maximum parallel clock is 125MHz
Therefore, the shortest latency in this mode is 13 clocks + 5.5 ns (from Table 4)
The "clock" in this case is 125Mhz/2 or 16ns
Therefore, the latency in this mode is 213.5ns
Is my interpretation of this datasheet correct?
