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RS-485 SN65HVD72 Half Duplex Questions

Dave Wills
Prodigy 30 points

Hi,

I have a question on this part in specific and RS-485 in general.  My application is half-duplex, multi-drop.  Typically, the bus will have all receivers.  Then a master will turn on its transmitter, send a message, then go back to receive.  One of the slaves will see its address, switch from receive to transmit, send a response, then go back to receive.

On the slave side, I'm disabling the transmitter then enabling the receiver.  This glitches the bus causing a start bit in all of the other receivers.  Is there a different sequence or something else which would eliminate the glitch and the false data byte?  For example, should I turn on my receiver, delay, then turn off my transmitter?  Is the glitch due to there being no transmitters enabled?

Thanks,

Dave

  • 0
    TI__Expert 5230 points

    Hello Dave,

    Are you disabling the slave's transmitter and enabling the receiver simultaneously?

    Is there a time delay between the master turning off it's transmitter and the slave responding? Could two nodes be driving the bus at the same time?

    Can you send an oscilloscope capture of the signals /RE, R, DE, D and also of VA, and VB during the disabling/enabling of the transmitter and receiver?

    Best Regards,

    Joe

     

  • 0 in reply to Joe Fockler
    Prodigy 30 points

    Hi Joe,

    Thanks for the reply.

    I've modified my transmit routine to the following sequence:

    - enable the transmitter

    - disable the receiver

    - delay 1 byte time to allow the receiver to flush bytes from false start bits

    - send my message

    - enable the receiver

    - disable the transmitter

    - delay 1 byte time in case a false start bit was received

    - flush the UART

    My master and all my slaves use the same function.  The slaves are all in receive mode except when replying to a master message, so there should not be 2 drivers on the bus at the same time, and most of the time there are no drivers on the bus.

    This works well, but the odd thing is the false start bit has gone away.  So I can't capture any logic analyzer screens to send.  I'm going to be working with this a little more and if I can capture a false start bit, I'll post again.

    Thanks for the reply.

    Dave

  • 0 in reply to Dave Wills
    TI__Mastermind 28265 points

    Dave,

     do you apply 120 ohm termination resistors at each bus end?

     

    Thanks, Thomas

  • 0 in reply to Thomas Kugelstadt
    Prodigy 30 points

    Hi Thomas,

    I was not involved in the hardware end of it, but I did check this out.  We're using 91 ohms because that's what the hardware guys determined was the impedance of the bus at the lengths and with the cabling we're using.  I have verified the resistors are in place.

    Thanks,

    Dave