I'm planning on evaluating a scan bridge circuit (SCANSTA112) on a prototype. The scan bridge will interact with a number of devices including FPGAs from Altera.
When I asked an Altera FAE whether using a scan bridge affects the JTAG-functionality of the FPGA, I received the following answer:
"Some customers have had problems with these devices when they interact with Altera tools and IP (like SFL or PFL). There should be no problems with boundary scan, and for the Altera stuff, it should be OK if you can out the bridge into a transparent pass-thru mode.
The reason for the problems with the Altera IP is that the bridge adds in an extra clock cycle shift which breaks some of the tools. I would advise you to speak to the TI apps engineer too to see what their experience is."
Does anyone have experience in this issue?
Emad
