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DS80PCI402 Power connection for VDD pins.

teejo jose
Prodigy 20 points

In the device datasheet, it is described that the device could be supplied with 3.3V and then use the internal voltage regulator to generate 2.5V or the device could be provided with 2.5V supply by bypassing the use of the internal voltage regulator.

I am using the device by providing the 3.3V supply and enabling the internal voltage regulators. As per the reference schematic, in this mode the VDD pins need to be connected to a .1uF capacitor to ground.

I have made a mistake in the schematic, i have shorted the VDD pins also to 3.3 V supply. Would this be a problem with respect to the operation of the device ?

  • 0
    TI__Guru* 93570 points

    This will damage the device. You may not see this right away  but within few days the device will be damaged since the 2.5V internal regulator is being over driven by 3.3V supply. Please cut the 3.3V trace going to the VDD pin.  

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 20 points

    Hi Nasser,

    Thank you for the information. I guessed the same because when i probed these pins after cutting the 3V3 track to the VDD pins I  observed 2.5V on the VDD pins. One further question regarding the same issue. The datasheet mentions a requirement of .1uF capacitor to be placed for each of the VDD pins. I am planning to  remove the connection of these VDD pins to the PCB. which effectively means i will not be providing these capacitors for this internally generated 2.5V. How critical are these capacitors with respect to performance of this device in PCIe Gen1/Gen2 operations ?

    Regards

    Teejo

  • 0 in reply to teejo jose
    TI__Guru* 93570 points

    Hi Teejo,

    I haven't seen this on this part but in general when there is noise or no DC coupling Caps on the reference supply then this may increase jitter. You may see this on some data pattern but not others so in the next revision please attach 0.1uF DC supply coupliong Cap.

    Regards,,nasser