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DS90CR288 split to multiple DS90CR287

Jim Suriano
Prodigy 30 points
Other Parts Discussed in Thread: DS90CR287

We have an application where we are using the DS90CR288 to deserialize CameraLink input data and split that to multiple DS90CR287 for retransmission. The DS90CR288 is functioning correctly and deseralizing the data properly, however the DS90CR287 is not generating proper LVDS outputs. From the data sheet it mentioned that the DS90CR287 shouldn't be enable until after the clock is available and we have delayed the turn on time of the chip appropriately but have still not gotten any output generated.


At this point we are not sure what else to try. We had another prototype board that functioned properly once we added the appropriate delay to turning on the DS90CR287 to account for the delay in the clock signal being generated (which we did through the use of a manual switch). We've since added a way to handle that automatically but that does not seem to have solved the issue.


Thanks,

Jim

  • 0
    TI__Genius 13475 points

    Jim

     

    A couple of things to try:

    Try powering up the DS90CR287, with the PWR DOWN pin held low, then once you are sure that you have a valid clock coming from the DS90CR288, then bring PWR DOWN high - the PLL should then lock and you should see activity on the LVDS outputs.

    Verify the CLK input to the DS90CR288 - make sure that it has the proper levels and is within the frequency range for the '288.

    Have you tried the circuit with only one DS90CR288 first, to make sure that it will lock, then adding the others to make your fanout function?

    Regards

     

    Mark

  • 0 in reply to Mark Sauerwald88474
    Prodigy 30 points

    Mark,

    Thanks for the info. I should have been a little more clear in my original description. We have a timer block that holds the PWR DOWN pin low during the period that the clock is not available and them turn PWR DOWN high after the clock is good. We have verified the outputs of the '288 and they look good. We haven't tried running just a single '287 chip in circuit at this point. I'd have to make some mods to the board to support that. I'd rather wait on that if there isn't any other options.

    Thanks,

    jim

  • 0 in reply to Jim Suriano
    Prodigy 30 points

    I have verified that our PWR DOWN signal is being pulled low during the startup period and goes high after the clock is good and available. I'm still looking for suggestions on how we might fix this issue. I can post relevant parts of the schematic if that would be useful.