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ISO7241CDW for SPI. Gate the enable pin off of CS?

Zachary Sloane
Prodigy 70 points
Other Parts Discussed in Thread: ISO7241C

I am using an ISO7241CDW to isolate an SPI bus. It seems as though there is an issue with the SPI SOMI line which I have connected to the "OUTD" (pin 6) of the unisolated side. When I am talking to the chip that is on the isolated side, everything works fine, but when I am trying to talk to something else on the unisolated side things don't work. The SOMI line is not pulled all the way low for a 0, thus basically I get all 1s for responses.

When I lift the pin 6 of the ISO7241 chip (unisolated SOMI) everything on the unisolated side works as expected. 

I have the SPI bus connected to the ISO7241 chip as follows:

Both EN1 and EN2 are tied to their respective VCC pins

CS1  --- PIN 3 (INA)            PIN 14 (OUTA) --- ISO_CS

CLK  --- PIN 4 (INB)            PIN 13 (OUTB) --- ISO_CLK

SIMO  --- PIN 5 (INC)            PIN 12 (OUTC) --- ISO_SIMO

SOMI  --- PIN 6 (OUTD)            PIN 11 (IND) --- ISO_CLK

Would gating the EN1 pin (with an inverter) off of the CS1 --- PIN3 (INA) pin rather than just always having it be high solve this problem?

Thanks

  • 0
    TI__Mastermind 21800 points

    Hi Zachary,

    When you say "When I lift pin 6 of the ISO7241 chip everything on the unisolated side works as expected", are you saying that when you look at the lifted pin it is pulling high and low as expected? As in SPI communication in both directions is working?

    This makes me think that there is something on the unisolated side of the system that is pulling high pretty hard. The outputs on the ISO7241 are capable of driving 4mA on the low level output current. Therefore if you are going into a standard pin on a micro controller, there should be no issue with driving the pin high or low.

    Could you share schematic / oscilloscope screenshot of the OUTD pin? It would be good to know if you have any pull-up resistors connected to this pin.

    Thanks,

    John

  • 0 in reply to John Griffith
    TI__Mastermind 21800 points

    Hey Zachary,

    Sorry for the second post, I was thinking about your question a little more this morning. Do you have only the SPI master on the non-isolated side, and the slave(s) are all on the isolated side?

    Or do you have a slave and master on the non-isolated side and an addition slave on the isolated side?

    I was trying to figure out from a system level if the isolated side is blocking communication on the non-isolated side.

    Thanks,

    John

  • 0 in reply to John Griffith
    Prodigy 70 points

    John,

    Thanks for your replies. I was away from my desk for a while so I haven't been able to respond.

    I'll try and explain how I have things setup:

    My DSP is setup as the SPI master. For the isolated part of things, there is only one device on the isolated side, which is a TI A/D. Then, on the non-isolated side of things, there are a number of other slave devices. A couple of I/O expanders, couple of SPI pressure sensors etc.

    The communication between the DSP and the isolated A/D is fine. However, the slave out data line seemed to only get pulled down about halfway when one of the unisolated slave devices intends to output a 0. For example on one of the I/O expanders I was testing I tied all of its pins except one high, which should have resulted in 0xFE but instead I got 0xFF. Once I lifted the pin on the ISO7241, I correctly get 0xFE from the unisolated slave I/O expander.

    EDIT: And the scope capture of the output shows the last bit trying to go low but only going halfway.

    Does that help?

    Thanks,

    Zack

  • 0 in reply to Zachary Sloane
    TI__Mastermind 21800 points

    Hey Zack,

    Yes it does. So i was picturing your system in my head differently and made some wrong assumptions. I think I see what is wrong now.

    EN1 controls all the output drivers on the VCC1 side (which in this case is only OUTD). EN2 controls all the output drivers on the VCC2 side, which for the ISO7241C device is OUTA, OUTB, and OUTC). Since you leave the EN1 pin tied high, the output of OUTD will either be driven high or low at all times depending on the state of IND. From your issue it sounds like when the isolated slave is not communicating the line is high, and therefore "fighting" the slaves on the non-isolated side.

    To fix this you will need to disable the OUTD output by pulling EN1 low. That way the pin will be high impedance and communication will occur on the non-isolated side without any issues.

    I think your idea of inverting the CS pin is exactly what you need to do. You have a dedicated CS for each slave device, so you just need to tie inverted level of the isolated SPI slave to the EN1 pin. That way EN1 is high when CS(isolated) is low, and communication will flow in both directions. Then when other slave are being addressed the isolated device is high impedance.

    Sorry I misunderstood the original set-up.

    Thanks,

    John

  • 0 in reply to John Griffith
    Prodigy 70 points

    John,

    Thanks for your help. I will make that change and see how it goes.

    ~Zack