• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Subscribers 33 subscribers
  • Views 670 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TL16C752C Initializing Interrupt

Miyauchi Eisuke
Prodigy 70 points
Other Parts Discussed in Thread: TL16C752C

Our customer has some problems. He wants to know that his code is correct.

Please help me how to solve his problem.


//Interrupts Disable 
base_adress+0x03(LCR) write 0xBF    ;for EFR access
base_adress+0x02(EFR) assert bit4   ;for IER[7:4], FCR[5:4],MCR[7:5] access  
base_adress+0x03(LCR) negate bit7   ;for IER access 
base_adress+0x01(IER) write 0x00 

//Init. FIFO(TX trigger 8spaces, RX trigger 1characters) 
base_adress+0x02(FCR) write 0x01  
base_adress+0x02(FCR) write 0x07   ; Clear FIFOs
base_adress+0x02(FCR) write 0x01 

//DATA :8bit, STOP bit: 1bit, Parity: no 
base_adress+0x03(LCR) write 0x03 

//Modem Control Setting (not use Autoflow) 
base_adress+0x04(MCR) write 0x00 

//Set Divisor Latches  
base_adress+0x03(LCR) assert bit7    ;for DLL/DLH access 
base_adress+0x00(DLL) write 0x03  ・・・①
base_adress+0x01(DLH) write 0x00

//Enable Interrupt (Temporary:All interrupts enabled except Sleep Mode.) 
base_adress+0x03(LCR) negate bit7     ;for IER access
base_adress+0x02(IIR) read            ;clear interrupt request　
base_adress+0x01(IER) write 0xEF 

//Data Sending 
500ms Sleep  ; for separate below phenomenon. 
base_adress+0x03(LCR) negate bit7　; for THR access 
base_adress+0x00(THR) write 0xAA  ・・・② 

<Phenomenon> 
・When process of ①, occur output on TX. 
  →Our customer think, assert bit7 just before LCR, so it to be DLL access, and isn't to be THR write. 
    （Output wave can't looks like 0x03） 
・When process of ②, occur output on TX, but output wave isn't 0xAA.

  • 0
    TI__Mastermind 36085 points

    Hello  Miyauchi,

       I saw the problem, in order to get access to the DDL/H registers, first You must set to 1 the bit7 of the LCR register, a suitable procedure is the following:

          1) Write 0x80 to LCR .

          2) Set the desire value to DLL and DLH.

          3)Write the desire configuration to LCR i.e. 0x03.

    NOTE: Remember that both channels on the TL10c752C are independents and must be configured separately.

     

    Best Regards,

    Diego.

  • 0 in reply to Diego Cortes
    Prodigy 70 points

    Dear Diego

    Thank you for your prompt reply.

    That is to say DLL/DLH setting is below, right?

    base_adress+0x03(LCR) write 0x80 
    base_adress+0x00(DLL) write 0x03 
    base_adress+0x01(DLH) write 0x00 
    base_adress+0x03(LCR) write 0x03   ←LCR resetting 
     
    If above is correct, is it same that it need assert particular bit of another register in order to access other register?
  • 0 in reply to Miyauchi Eisuke
    Prodigy 70 points
    My customer change how to register bit, but trouble output waveform is no change.
    Could you advice and help please?
    ■DLL/DLH setting
    [Before] 
    base_adress+0x03(LCR)write(Present value |= 0x80)（LCR[7] = 1） 
    base_adress+0x00(DLL) write 0x03 
    base_adress+0x01(DLH) write 0x00 

    [Now] 
    base_adress+0x03(LCR)write 0x80（LCR[7] = 1） 
    base_adress+0x00(DLL) write 0x03 
    base_adress+0x01(DLH) write 0x00 
    base_adress+0x03(LCR) write 0x03 （LCR resetting） 

    【Trial result】 
    ・Occur trouble output waveform at TX in DLL access timing.
    ・Occur trouble output waveform at TX in THR access timing.
    Attached file: Purple line is trouble output waveform.
    　　　
  • 0 in reply to Miyauchi Eisuke
    TI__Mastermind 36085 points

    Hello Miyauchi,

        Let's try the chip configuration since the beginning, You only add the loopback feature to Your configuration ( for a normal operation, just omit the line where MCR is equal to 0x10).

    Turn ON the UART system (or power cycle it) and make sure You are NOT accessing to the configuration addresses before the following steps:

    LCR (Base_Address + 0x03) = 0x80

    DLL (Base_Address + 0x00) = 0x03

    DLH (Base_Address + 0x01) = 0x00

    LCR (Base_Address + 0x03) = 0x03

    IER (Base_Address + 0x01) = 0xEF

    READ IIR (Base_Address + 0x02)

    FCR (Base_Address + 0x02) = 0x07

    MCR (Base_Address + 0x04) = 0x10

    --------Now test the functionality, sending and receiving is done by the same channel (Base_Address + 0x00) and checking the LSR (Base_Address + 0x05).

    I attached a successful example using the EVM of the TL16C752C,  running on DOS (Base_Address = 0x300).

     IMPORTANT NOTE: I omitted some of Your steps because You are using the default values (see the table 2, page 11 on the datasheet) .-

    Best Regards,

    Diego.

    6763.TL16C752C config.pdf

  • 0 in reply to Diego Cortes
    Prodigy 70 points
    Dear Diego san
    Thank you for your reply.
    My customer tried through your reply.
    But it is not good behavior.
    Could you teach below question?
    ＜Trial content＞ 
    Confirm sending and receiving through below setting.

    LCR (Base_Address + 0x03) = 0x80 
    DLL (Base_Address + 0x00) = 0x03 
    DLH (Base_Address + 0x01) = 0x00 
    LCR (Base_Address + 0x03) = 0x03 
    IER (Base_Address + 0x01) = 0xEF 
    READ IIR (Base_Address + 0x02) 
    FCR (Base_Address + 0x02) = 0x07 
    MCR (Base_Address + 0x04) = 0x10 
    500ms sleep (to separate setting handling) 
    THR (Base_Address + 0x00) = 0xAA (0xAA sending) 
    100ms sleep (It don't know time until sending loop back) 
    READ LSR (Base_Address + 0x05) 
    READ RHR (Base_Address + 0x00) 

    ＜Trial result＞ 
    ・After setting until MCR, the case is reading LSR and RHR MCR, condition is not sending(WRITE THR)).
        LSR = 0xEF 
        RHR = 0x00 
    ・After setting until MCR, the case is reading LSR and RHR MCR, condition is sending(WRITE THR)).
        LSR = 0xEF 
        RHR = 0x2A 

    ＜Remark＞ 
    ・LSR is always assert except bit4. 
      (bit4=0:No break condition) 
    ・bit0 of LSR assert without sending. 
      (bit0=1:At least one character in the RX FIFO) 
    ・0xAA sendingm but motion is receiving. Data is 0x2A. 
    Best Regards,
    Eisuke Miyauchi
  • 0 in reply to Miyauchi Eisuke
    Prodigy 70 points

    Sorry, my customer update their requests.

    Could you teach us what is problem at this time request?

    ①＜Trial content and result＞ 
    Below is execute result of log output. 
    (Base_Address = 0xB8000000) 

    [W] LCR addr:0xB8000003 val=0x80 
    [W] DLL addr:0xB8000000 val=0x03 
    [W] DLH addr:0xB8000001 val=0x00 
    [W] LCR addr:0xB8000003 val=0x03 
    [W] IER addr:0xB8000001 val=0xEF 
    [R] IIR addr:0xB8000002 val=0x01 
    [W] FCR addr:0xB8000002 val=0x07 
    [W] MCR addr:0xB8000004 val=0x10 
    [R] LSR addr:0xB8000005 val=0xEF 
    [W] THR addr:0xB8000000 val=0xDA 
    [W] THR addr:0xB8000000 val=0xDB 
    [W] THR addr:0xB8000000 val=0x0A 
    [W] THR addr:0xB8000000 val=0x1B 
    msleep(200) 
    [R] RHR addr:0xB8000000 val=0x1A 
    [R] RHR addr:0xB8000000 val=0x1B 
    [R] RHR addr:0xB8000000 val=0x0A 
    [R] RHR addr:0xB8000000 val=0x1B 
    [R] RHR addr:0xB8000000 val=0x00 
    [R] RHR addr:0xB8000000 val=0x00 
    [R] LSR addr:0xB8000005 val=0xEF 
    [W] THR addr:0xB8000000 val=0xAA 
    [W] THR addr:0xB8000000 val=0xAB 
    [W] THR addr:0xB8000000 val=0xAC 
    [W] THR addr:0xB8000000 val=0xAD 
    msleep(200) 
    [R] LSR addr:0xB8000005 val=0xEF 
    [R] RHR addr:0xB8000000 val=0x2A 
    [R] RHR addr:0xB8000000 val=0x2B 
    [R] RHR addr:0xB8000000 val=0x2C 
    [R] RHR addr:0xB8000000 val=0x2D 
    [R] RHR addr:0xB8000000 val=0x00 
    [R] RHR addr:0xB8000000 val=0x00 
    [R] LSR addr:0xB8000005 val=0xEF 

    ＜Remark＞ 
    My customer care below things compare your trial result. 

    ・IIR read result, Diego san is 0x02, but my customer is 0x01.
      →This is cause of interrupt clear, so it is no relation? 
    ・LSR read result is everytime 0xEF. 
      →Almost error bit assert. 
    ・RHR read result is not consensus THR write content.
      →Head 2 bit looks like down. 
        0xDA(1101 1010) → 0x1A(0001 1010)
     
     
    ②About interrupt
    ＜Trial content＞ 
    My customer setting below 2 pattern, and confirm each pattern whether assert interrupt.
    (Base_Address = 0xB8000000) 

    [Pattern 1(before we are taught from you.)] 
      LCR(base_adress+0x03)  =  0xBF 
      EFR(base_adress+0x02) |=  0x10 (bit4 assert) 
      LCR(base_adress+0x03) &= ~0x80 (bit7 negate) 
      IER(base_adress+0x01)  =  0x00 
      FCR(base_adress+0x02)  =  0x01 
      FCR(base_adress+0x02)  =  0x07 
      FCR(base_adress+0x02)  =  0x01 
      LCR(base_adress+0x03)  =  0x03 
      MCR(base_adress+0x04)  =  0x00 
      LCR(base_adress+0x03) |=  0x80 (bit7 assert) 
      DLL(base_adress+0x00)  =  0x03 
      DLH(base_adress+0x01)  =  0x00 
      LCR(base_adress+0x03) &= ~0x80 (bit7 negate) 
      READ IIR(base_adress+0x02) 
      IER(base_adress+0x01)  =  0xEF 

    [Pattern 2(this is correspond your attached sample file last time.)] 
      LCR(base_adress+0x03)  =  0x80 
      DLL(base_adress+0x00)  =  0x03 
      DLH(base_adress+0x01)  =  0x00 
      LCR(base_adress+0x03)  =  0x03 
      IER(base_adress+0x01)  =  0xEF 
      READ IIR(base_adress+0x02) 
      FCR(base_adress+0x02)  =  0x07 
      MCR(base_adress+0x04)  =  0x10 


    ＜Trial result＞ 
    ・After pattern 1 setting 
      →Not assert interrupt (they wish sending empty) 
    ・After pattern 1 setting, from a countering machine sending data (self machine receiving) 
      →Not assert interrupt (they wish there is receiving data.) 
    ・After pattern 2 setting 
      →Not assert interrupt (they wish sending empty)  
    ・After pattern 2 setting, from sending to receiving.(loop back) 
      →Not assert interrupt

    Through above, not assert interrupt...
    Best Regards,
    Eisuke Miyauchi
  • 0 in reply to Miyauchi Eisuke
    TI__Mastermind 36085 points

    I am concerned about the customers result. It seems to be a problem related to the communication between the CPU and the TL16C752C. Could You try to reproduce the code attached to confirm a proper device function?.

    Another question, Which interrupt are you trying to activate? because I noticed that You are enabling all the interrupts, even if You are not using the modem control lines.

    Best Regards,

    Diego.

  • 0 in reply to Diego Cortes
    Prodigy 70 points

    Dear Diego san

    Thank you for your prompt reply.

    My customer tried your attached code, but it is not clearly...

    What is a cause? Could you teanch us, please?
    ＜Trial result＞ 

    [R] LSR addr:0xB8000005 val=0x00  …① 
    [R] IIR addr:0xB8000002 val=0x01 
    [W] IER addr:0xB8000001 val=0xEF 
    [R] IIR addr:0xB8000002 val=0x01  …② 
    [R] IIR addr:0xB8000002 val=0x01 
    [W] LCR addr:0xB8000003 val=0x80 
    [W] DLL addr:0xB8000000 val=0x03 
    [W] DLH addr:0xB8000001 val=0x00 
    [W] LCR addr:0xB8000003 val=0x03 
    [W] IER addr:0xB8000001 val=0xEF 
    [R] IIR addr:0xB8000002 val=0x01  …③ 
    [R] IIR addr:0xB8000002 val=0x01 
    [W] FCR addr:0xB8000002 val=0x07 
    [W] MCR addr:0xB8000004 val=0x10 
    [R] LSR addr:0xB8000005 val=0xEF  …④ 

    ＜Remark＞ 
    ①Initial value is different from your execute result and my customer's. 
    ②It is not to be interrupt situation
    ③It is not to be interrupt situation as same ② 
    ④Unlike your execute result, two or more error assert. 

    Best Regards,
    Eisuke Miyauchi

  • 0 in reply to Miyauchi Eisuke
    TI__Mastermind 36085 points

    Hello Eisuke,

        I noticed there is a problem with the UART implementation and We can follow up by two ways, one is to review the physical implementation starting from the schematic, and the other one is to confirm that Your design complies in a stable way the following requirements:

    Best Regards,

    Diego.

  • 0 in reply to Diego Cortes
    Prodigy 70 points

    Dear Diego-san

    Sorry for late this reply. Thank you for your reply.

    My customer seems solve this problem.

    If there will be occur some problems, please support again.

    Best Regards,

    Eisuke Miyauchi