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Questions regarding to TFP410 CTLpins, etc

David888888
Intellectual 420 points

In my design, I am using low-swing mode for (DATA[23:0], DE, HSYNC, VSYNC, and IDCK±) and my Vref setting point is at 0.9V.

Does this means the input voltage range for above pins are 1.8V max?

If  above information is  true, how about the input voltage range for SDA, SCL, CTL1,2,and 3 pins?

Are they all +3.3V or +1.8V?

Many thanks.

  • 0
    TI__Guru* 76130 points

    Hello,

    For your first question: yes, VREF should be set to the half of the input voltage, if VREF is 0.9V then your inputs should be 1.8V.

    According with the datasheet, VREF only affects DATA[], DE, HSYNC, VSYNC and IDCK so SDA, SCL and CTL[] are 3.3V only.

    Regards.

  • 0
    Prodigy 210 points

    In low swing mode , input thresholds for (DATA[23:0], DE, HSYNC, VSYNC, and IDCK±) are

    Vih = Vref +0.2V and

    Vil = Vref - 0.2V.

    It is only for input threshold. It does not limit the maximum voltage swing. You can still drive those inputs with 3.3V signals if you only have 3.3V level.