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Auto nego and Link Failure, TLK110

Suno Kim
Prodigy 170 points
Other Parts Discussed in Thread: TLK110

Hi,

I designed C6743 ank TLK110 combination for ethernet interface. and I tried to LINK setup but failed.

I designed it with soft bootstrap, and after hardware reset I tried,

 1. HW Reset

 2. Read OUI(2h) until data is 0x2000

 3. SWSCR1 =  SWSCR1 | AUTOMIX_EN | AUTONEGO_EN | AN_1 | AN_0 | BOOT_LED

 4. SWSCR1 =   SWSCR1 | CONFIG_DONE

 5. RSCR = RSCR |  RMII_MODE | ELAST_BUF=2

 6. Delay(200ms)

 7. While(1)

    BMCR = BMCR  |  Restart Auto-Neg

    Delay(4000ms)

    If Restart Auto-Nego == 0, break Loop

 8. Check Auto Nego Complete, BMSR  <--- Failed

 9. Check Link Status, BMSR       <--- Failed

 

What  I  should do to complete Auto Nego and Link?

And I doubt, in TLK110 manual, "Restart Auto-nego" is self clearing bit. and why Auto Nego Complete bit  in BMSR is not set, after this bit cleared.

Please let me know how to Link.

 

Thank You.

  • 0
    TI__Intellectual 1885 points

    Hello,

    I have a few questions regarding your setup.

    What link partner are you trying to link to?

    Are you using straight or cross ethernet cables?

    Can you read the registers of the TLK110?

    If you can read them, can you get a register dump of the TLK110?

    Are you hardware strapping the PHY?

    Thank you,

    John

  • 0 in reply to John Hamilton1
    Prodigy 170 points

    Hello, John

    Link Partner : 3com Gigabit Switch 5, Model 3CGSU05A, 2010-02-27 produced.

    Same Color, Straight Cable.

    Yes I can and Register written below is all Hex format (offset : value)

    000:3100

    001:7849

    002:2000

    003:A211

    004:01E1

    005:0000

    006:0004

    007:2001

    008:0000

    009:FC01

    00A:0105

    00B ~ 00F:0000

    010:0002

    011:010B

    012:0000

    013:0800

    014:0000

    015:0000

    016:0100

    017:0001

    018:0400

    019:8021

    01A:0000

    01B:007D

    01C:05EE

    01D:0000

    01E:0102

    01F:0000

    042:2000

    0D0:0002

    155:0000

    170:0002

    171:010B

    172:0000

    173:0000

    177:0001

    180:3100

    181:7849

    182:2000

    183:A211

    184:01E1

    185:0000

    186:0004

    187:2001

    188:0000

    189:FC01

    18A:0105

    18B:0000

    No I use software strapping - SW_STRAP is pull downed with 2.2kOhm

    but, Hardware condition is : Pin11 - Pull down 2.2kOhm.  Pin 18, Pin 39, Pin30 - Pull Up 2.2kOhm

    and I could see the similar wave form as "Figure 2. Link Pulse Waveform" in slla327.pdf, after I did configuration,  at TD+ and TD- pin.

    but the pulse has half width, and half period than RD+/RD- signal come from 3Com switch.

    It seemed TLK110 operating in MII mode with 50MHz clock. (not divide 1/2). Is it right?

    And do you know why the pulse signal from TD+ is negative pulse and TD- has positive pulse? and how to change it?

    Thank You,

    Suno

  • 0 in reply to Suno Kim
    Prodigy 170 points

    Thanks John Hamilton,

    I've just solved my problem.

    The key point is MII_MODE(RX_DV) pull-up (It was pull downed).

    I read  this mode selection at the "3.1 Bootstrap Configuration" chapter in the TLK110 manual.

    so, I understand that if I use "Software Strapping Mode"  those Bootstrap configuration could be changed.

    But, RMII mode negotiation only can be done with hardware MII_MODE bootstrap!

    Thanks again for your concerned for me.

    Suno.