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LMH0340 - LVDS Switching Characteristic

Kawai
Guru 19785 points
Other Parts Discussed in Thread: LMH0340

Hi Team,

Our customer is considering to use LMH0340. Could you please tell us about the following timing specification ?

Q1)
There is an electrical specification of "tXIT" (TxIN Transition Time). Is this spec for 20% to 80% or 80% to 20%of the rise/fall time ?

Q2)
There is an electrical specification of "tSTC" and "tHTC" for setup and hold timing.
For tHTC, I understood that MIN 900ps is needed for HOLD time, but for tSTC there is a value of -550ps(MIN).
This MIN and "-" is a little bit confusing but does this mean that the device needs more than 550ps for setup time ?

Best Regards,

Kawai  

  • 0
    TI__Genius 13475 points

    Q1)  Yes, Txit is the 20-80 transition time for the DATA inputs, and corresponds to Tcit for the TX CLK input.

    Q2) The Setup and hold times are confusing.   For the device to latch data properly, the data must be stable for tSTC before the clock edge, and must remain stable until tHTC after the clock edge.  In the case of the LMH0340, tSTC is a negative number, which means that as long as the data is stable from the point 550ps AFTER the clock edge until 900ps AFTER the clock edge, then the data will be latched correctly.   This is with the default setting in register 030h, this window can be shifter closer to, or further from the clock edge by changing the value in the MSBs of register 030h

     

  • 0 in reply to Mark Sauerwald88474
    Guru 19785 points

    Mark-san,

    Please let me confirm one thing to Q2.

    Your answer says,
    "tSTC is a negative number, which means that as long as the data is stable from the point 550ps AFTER the clock edge until 900ps AFTER the clock edge, then the data will be latched correctly."

    I think it was your typo but tSTC should be 550ps "BEFORE" the clock edge, am I correct ? The data must be stable for more than 550ps BEFORE the clock edge.

    As an example, if tSTC is -500ps,  which is 500ps BEFORE the clock edge is not recommended.

    Best Regards,
    Kawai

  • 0 in reply to Kawai
    TI__Genius 13475 points

    Kawai-san

    No typo - the negative sign indicates that the opening of the stable period is AFTER the rising edge, if there were no negative sign, then the signal would have to be stable 550ps BEFORE the edge, resulting in a requirement that the signal remain stable for a total of 1.45ns.   In fact, the input signal only needs to remain stable for 350ps in order for the device to operate properly.

    Mark Sauerwald

     

  • 0 in reply to Mark Sauerwald88474
    Guru 19785 points

    Mark-san,

    I apologize for my misunderstanding.

    I found the Application Note AN-1988 which describes well about the LVDS timing.

    http://www.ti.com/litv/pdf/snla122a

    So, this is done by the delay circuit in the TCLK line, which is programmable.

    Best Regards,

    Kawai