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TCA9406 internal pullups not working properly

Other Parts Discussed in Thread: TCA9535, TCA9406

I've got a simple I2C interface design in prototyping, and due to the slow speed of our I2C implementation (10 KHz max) and short runs, I opted to use the internal 10K pullups in this part. However, in prototyping, with OE pulled high and no loads on inputs or outputs, the pullups only produce an approximate 2.2 volt output, which is in error, as the pullups are supposed to go to the rail of the appropriate side. I can't find if this part has any errata on it, and the behavior I report has been observed with more than one part. The basic design is a 3.3V (VCCA) to 5.2V (VCCB) translator, with a TCA9535 as the only device on the 5.2 volt side. The power supplies are zener-clamped in the prototype phase, and have not been observed to overshoot anyway. OE is tied to 5.2V. Unfortunately, I did not include optional pullups due to space availability, and leaving the TCA9535 I2C inputs at 2.2 volts causes the device to pull some 30 ma from the 5.2 volt rail, which is not the case if the inputs are pulled fully up to 5.2V! Even with the TCA9535 removed (no device on either the 3.3 or 5.2 volt rail I2C bus), the pullups only pull to 2.2 volts on both sides! Logically, minus the pullup issues, the device does pass logic signals, just at the wrong voltage levels due to the pullup voltage. Our devices were samples, marked with "NFER", in the VSSOP package.

  • David,

    I am looking into this problem for you, I will get back to you as soon as possible. 

    Regards,
    Chris Kraft 

  • Thanks. I've tried two ICs so far, and each behave identically. Pullups appear to give around 2.2 volts on both VCCA and VCCB, with no external loads, with the power supplies verified as 3.3v (A) and 5.2V (B). The circuit does pass data from side to side, just to the wrong pullup voltage.

  • Any updates? The design, which was supposed to be a slam-dunk prototype, is on hold, and our management is applying pressure for when things will be moving again, or whether the design will have to be recast for the NXP translator part. Thanks.

  • Hi David,

    I apologize for the delay.

    My first suggestion is to try to disconnect OE from the 5.2V rail and instead connect it to the 3.3V rail. OE is referenced off of VCCA and all of the ESD structures are designed with the assumption that OE will not be higher than VCCA.

    Please let me know if this corrects the issue or not.

    Regards,
    Chris Kraft

  • I'll lift the OE pin and give this a try., although scabbing the jumper to VCCA will be a bit difficult at this time. The data sheet mentions that the logic level is referenced to VCCA, but that OE's withstand is 6.5V if I'm correct. No mention of ESD structures referenced to VCCA, which probably should be corrected. Is it likely the part I have onboard has been compromised in the process so I have to replace the whole part? I've about burned through my TI sample pile trying to figure this problem out by now. Thanks.

  • I just lifted OE on the part I currently have onboard and tied it to 3.3. No change. Both sides still pull up to 2.2 volts or so. The chip does pass data (you pull any pin low and the corresponding pin on the other side of the device goes low). The pullup voltage is the issue. Why 2.2 volts, I have no idea, as VCCA and VCCB are accurate.

  • Hi David,

    I want to ensure that I understand all the conditions that have been tested so far. Please correct me if I have anything wrong

    Under all the conditions VCCA  = 3.3V and VCCB = 5.2V

    • With I2C master and TCA9535 connected, OE = 5.2V, SDA_A/SCL_A & SDA_B/SCL_B are all at 2.2V
    • With I2C master and TCA9535 disconnected (ie SDA/SCL are floating) OE = 5.2V, the voltage at SDA_A/SCL_A & SDA_B/SCL_B are still 2.2V
    • With the voltage of OE changed to 3.3V,  SDA_A/SCL_A & SDA_B/SCL_B are still 2.2V
    Would you be willing to share a screen shot of the PCB layout where the TCA9406 is being connected to?
    When you said that the chip passes data in the most recent post, on the rising edge does the output overshoot to the respective rail or does it just rise to 2.2V?
    Regards,
    Chris Kraft 
  • You are correct in your assumptions, with the exception that there never has been an I2C master connected to the board. The board never got far enough in prototype evaluation to mate up with a master.

    I haven't scoped any overshoot when switching data levels--that sounds like a great task to do next. I'll see and let you know. What forms can you take the layout or schematic in? I don't mind sharing (and I have a few bare laminates to take pics of, but a really poor camera (iPad) to use. I can also screenshot my PCB layout package as well. The board is a two layer laminate. I'm also not sure how to send pics via the E2E system here.

    Thanks.

  • I'd also be happy to do a Teamviewer or other remote display service so a TI person could come in and review the layout electronically in real time with me. That might be better than throwing pics over the transom. The layout and schema is really quite simple. I'm heading out to the lab to hook up a sig gen and a open collector driver to the I2C.

  • David,

    I can view Altium, Cadence and Pads designs otherwise you can just export it to PDF or take a screen shot of the PCB layout. To send pictures or files you will use the insert picture or insert file button that is circled below.

     

    Regards,
    Chris Kraft 

  • Here is an Altium PDF of the design. Without an NDA, it will be difficult to send the actual layout files.

  • I did insert the PDF and saw the link before posting, but cannot see it in the resulting post, so please confirm that you can see it as a TI employee. Thanks.

  • Hi David,

    I cannot see the PDF. Try just posting a picture of the area that might work instead.

    Regards,
    Chris Kraft 

  • I'll try posting the PDF one more time, and use IE this time rather than Firefox. Also, since we talked last, I tried several things--I put 3.3K external pullups in, but the chip is still pretty insistent on pulling the inputs to around 2.2 to 2.3 volts regardless. I'm working on overshoot observations.8816.Handheld.pdf

  • Chris, this troubleshooting and E2E problem resolution system is not working. I'm stuck on hold with this proto now for over a week. I'm convinced, after trying yet the third sample (and my last on-hand) on the board, making sure OE never sees more than 3.3 volts and zener clamping VCCA and VCCB just in case, AND seeing the same results, that this part is defective. Whether the 3 samples I received from TI were defective, or this part has had a defective lot manufactured that my samples came from, I can't tell you. My application is as simple as they come, and the part appears to have the logic I/O on both VCCA and VCCB sides internally pulled up to around 2.2 volts. I'd like to speak with someone from this product group and also receive some samples that TI positively KNOWS are from a good lot. My phone number is 319-393-5200 x305. I look forward to the call. I can escalate through disty FAEs too, if that would get resolution faster. I need to get this project off my plate. Thank you.