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DS110DF111 - Interrupt bits

Kawai
Guru 19785 points

Hi, I have a question about the interrupt signal in the register.

In the datasheet  P.14 "Interrupt Channel Flag Bits", there says detail description is explained on the section "Interrupt handling" but there is no such section.

Could you please give us explanation for interrupt status bits for DF111 and how to clear these bits, ?

I think the followings are the DF111 interrupt register bits. Please confirm if my recognition are correct.

-----

<Control and Shared Register>
ADR 0x05 Bit3 : Channel A Interrupt
ADR 0x05 Bit2 : Channel B Interrupt

When are these bit set ?

How do you clear these bits ?
When ADR 0x05 is read or when the ADR which describes detail interrupt information in channel register ?

-----

<Channel Register>
ADR 0x01 bit4 : CDR Lock Loss interrupt
  -> Set when Lock loss. It is cleared when this register address is read.
       If you want to see current status, you would need to read twice.

ADR 0x01 Bit1 : Signal Detect Loss Interrupt
  -> Set when input signal is loss. It is cleared when this register address is read.
       If you want to see current status, you would need to read twice.

ADR 0x30 bit4 : Goes high if interrupt from CDR Goes High
  -> What do you mean by interrupt from CDR ? HEO/VEO Interrupt ?? (If not which shows HEO/VEO Interrupt ?)
  -> How do you clear this bit ?

-----

Best Regards,
Kawai

  • 0
    TI__Guru* 93670 points

    Kawai-San,

    1). To clear the interrupt we should read the register and this would clear up the interrupt. The following example could provide a short over view of the procedures to see how this is done. For example, we would like to setup the HEO-VEO to cause interrupt when a threshold is reached. Here are different steps:

    1- Setup the HEO-VEO Thresholds(Reg 0x032 & 0x033)

    2- Enable LOS to be used as interrupt(Reg 0xFF[5])

    3- Enable HEO-VEO Interrupt(Reg 0x36[6])

    4- Once interrupt occur(Reg 0x030[4]), to clear the interrupt, we should read register 0x30

    5- If HEO-VEO is still causing interrupt, the interrupt will not clear until HEO-VEO is below the threshold.

    6- You can disable the interrupt source, for example in this case, HEO-VEO(Reg 0x36[6]), so it will not generate interrupt.

    Hope this will give you a good understanding of the interrupt operation.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Guru 19785 points

    Nasser-san,

    Thank you for the explanation.

    It was a great help.

    Best Regards,

    Kawai