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PCIe to PCI Bridge XIO2000a sends PE_PME messages

Viktor Bergen
Prodigy 130 points
Other Parts Discussed in Thread: XIO2000A

Hello,

We are using the XIO2000a PCIe to PCI Bridge for many years.

Now we discovered that when the XIO2000a receives a message Set_Slot_Power_limit of 0 Watt it starts sending PM_PME messages to the root complex every 100ms and after 30sec the whole communication stops. My understanding is that the XIO2000a should not send PM_PME messages in this case as it is programmed to ignore slot power limit in the POWER_OVRD register (reg. D4h bits 20-22 = 000b). I also verified that the PME\ pin has a pull-up.

Could you please help to resolve this?

Best regards,

Viktor

  • 0
    TI__Guru* 76130 points

    Hello,

    We are reviewing your issue, can you send a PCI register dump in order to replicate your set up.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 130 points

    Hello Elias Villegas,

    Thank you for taking care about this issue.

    Since the system does not boot, I cannot dump the registers.Please find attached the register settings of the EEPROM file.

    Fullscreen 2772.XIO2000A-wnv.txt Download 
    00	00	00000000
01	1E	00011110
02	78	01111000
03	56	01010110
04	34	00110100
05	12	00010010
06	00	00000000
07	C0	11000000
08	06	00000110
09	82	10000010
0A	37	00111000
0B	00	00000000
0C	00	00000000
0D	40	01000000
0E	00	00000000
0F	40	01000000
10	00	00000000
11	00	00000000
12	00	00000000
13	08	00001000
14	01	00000001
15	12	00010010
16	00	00000000
17	00	00000000
18	60	01100000
19	14	00010100
1A	32	00110010
1B	00	00000000
1C	00	00000000
1D	00	00000000
1E	00	00000000
1F	00	00000000
20	01	00000001
21	17	00010111
22	42	01000010
23	12	00010010
24	34	00110100
25	56	01010110
26	78	01111000
27	02	00000010
28	00	00000000
29	56	01010110
2A	28	00101000
2B	00	00000000
2C	08	00001000
2D	34	00110100
2E	97	10010111
2F	01	00000001
30	00	00000000
31	00	00000000
32	10	00010000
33	08	00001000
34	08	00001000
35	00	00000000
36	00	00000000
37	00	00000000
38	08	00001000
39	80	10000000

    I also captured everything what happens on the PCIe bus with a LeCroy PCIe analyzer. I stored the capture file at http://pgog6x.1fichier.com/en/. You can view it with the PETracer Software version 6.65 available on teledynelecroy.com website.

    Regards,
    Viktor

  • 0 in reply to Viktor Bergen
    TI__Guru* 76130 points

    Hello,

    This could be caused by an incorrect power-up or sequence, please check you are following the power-up sequence described on the datasheet.

    Connect Vuax to the 3.3V rail and connect PME# to that same rail.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 130 points

    Hello,

    In our layout the VAUX signal from PCIe connector pin B10 is connected to pin K14 on the XIO2000a (VDD_33_AUX). This VAUX is also used as pull-up over 4.7K Ohm for the PME\ pin M15. I reviewed the documentation and do not see why this should be wrong. I also checked the schematics of the evaluation board XIO2000aEVM. There it is connected the same way.

    Now for testing I cut on our board the VAUX from the PCIe connector and connected it to 3.3V (Pin B8 on the PCIe connector). This did really helped and the problem disappeared.

    Does it mean we should always not use VAUX from the PCIe connector? Why should we do it that way? Is there a documentation for this? Is for this a different workaround that does not require a layout change possible (maybe a different setting of the EEPROM)?
    Thank you.

    Regards

  • 0 in reply to Viktor Bergen
    TI__Guru* 76130 points

    Hello,

    Normally the PME# pin should be connected to Vaux, but I've seen some system that don't implement the Vaux properly, this means that Vaux is not compliant with the specification when the system is powered-down, this seems to be your case.

    Another reason for the bridge sending PM_PME messages is an incorrect power-up or power-down sequence, please review the datasheet and check that you are following these power up/down sequences.

    In other words, the bridge will work just fine if the system implement the Vaux correctly and if you follow the power sequences, but also, the above workaround should not present any issue to the system.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 130 points

    Hello,

    In this specific system Vaux comes up 2ms after 3.3V. Obviously this causes the problem.
    I’m trying to understand where the error is. On most systems Vaux is present before 3.3V comes up. However in the PCIe specification I could not find that this is required. It actually seems to be allowed not to provide Vaux at all.

    My question now is what is the correct implementation of the XIO2000a? Is it recommended always not using Vaux from PCIe connector and use 3.3V on the PCIe card instead?

    Regards

  • 0 in reply to Viktor Bergen
    TI__Guru* 76130 points

    Hello,

    It depends on your needs. Vaux is required when the bridge needs to be able to wake the system up from a power saving state where the system will remove the 3.3V power.

    If this is not your case, then you should connect Vaux to Vss through a resistor greater than 3K.

    If you need Vaux power, then as you said the problem should be that Vaux is coming up too late, in this case I think you can connect Vaux to 3.3V with no issues.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 130 points

    Hello,

    This answeres my question. Thank you for the help!

    Regards.