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TPD2E009DRTR VBR

WhiteHorse
Genius 4430 points
Other Parts Discussed in Thread: TPD2EUSB30A, TPD4E002, TPD4E1U06

We have a customer with some FPGAs damaged by ESD they believe.  They say:

"We are using the TI  TPD2E009DRTR  2-CHANNEL ESD SOLUTION FOR HIGH-SPEED (6 GBPS) DIFFERENTIAL INTERFACE on our SATA drives and have seen some blown FPGA transceivers on RMA units which we believe is due to ESD events.

 We put the parts on a curve tracer and the clamp doesn’t seem to kick in until near 12 Volts.  Why is it set to clamp at such a high voltage for differential signals that should never exceed 2 Volts per the SATA specification?."

Can you suggest some reasons the customer is seeing a VBR over 12 volts when it should be 12V.  I have let them know the TPD2EUSB30DRTR is identical except VBR is 4.5V.

Thanks for your help.

  • 0
    TI__Guru 71526 points

    Your observations are correct.  The purpose of the ESD protector is to dissipate the energy of the ESD event, rated in terms of A/usec, not as a voltage.  If you look at Fig 6 in the datasheet, you'll see the initial pulse is 15V.  Also note the MIN VBR is 7V (pg 3).  By comparison, the TPD2EUSB30A has a VBR of 4.5V MIN (no MAX specified).

    Alternatively, the TPD4E1U06 has a VBR of 8.5V MAX, and the TPD4E002 is 7.2V MAX.

    -Leonard