My customer is looking at using the TI DP83620 ethernet PHY in one of our designs using 2v5 logic to drive the RMII bus. According to the datasheet, this device is able to be driven by 2v5 or 3v3 logic (depending upon the VDDIO voltage applied). However when we look at the evaluation board schematic they only drive it with 3v3 logic and have a MII interface port which may be supplied with 3v3 or 5v.
I was wondering if it would be possible to get it confirmed that this chip is actually fine to work with 2v5 logic?
