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About the power sequence of DP83865

Satoshi
Guru 19645 points
Other Parts Discussed in Thread: DP83865

Please let me know about the power sequence of DP83865.

 

Although back 2.5V/3.3V (V I/O) which started 1.8V (V core) is started,

 if there is a recommendation range (??ms~??ms) about delay time in the sequence,

please let me know.

 

Thank you for your consideration.

  • 0
    TI__Intellectual 1885 points

    Hello Satoshi,

    As per the Data Sheet section 5.12:

    '

    During power-up, the power supply voltages are not available

    immediately but ramp up relatively slow compared to

    the clock period of the system clock (CLOCK_IN). How

    quickly a supply voltage reaches the “power good” level of

    typically 95% of its nominal voltage varies from design to

    design.

    There is no specific requirement for power-up sequence for

    the DP83865. However, if it is desirable to control the

    power up order, it is theoretically advised to power up

    CORE_VDD supply first. If there is no such ability all supplies

    can be powered up at the same time. There is no

    known sequence to date that can cause DP83865 in a

    latch-up or lock up condition.

    In any event, the RESET signal should be held low until

    after all power supplies have reached their nominal voltages.

    See Section 6.2 for additional requirements.'

    I hope that this addresses your questions.

    Thanks,

    John

  • 0 in reply to John Hamilton1
    TI__Mastermind 31600 points

    Satoshi,

    I moved this post to the Ethernet forum to make sure that it gets visibility from the right technical experts.  Going forward, the Ethernet forum will be the best place for posts related to the TLK1xx and DP83xxx devices.

    Based on the feedback provided in the previous post, it sounds like your question may be resolved.  If so, please don't forget to verify answers to your forum questions by using the green "Verify Answer" button.

    Patrick