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DP83460 Does not recognize an event

We are using a DP83460 PHYTER Ethernet chip. I enabled the event time stamp through the event configuration register at page 5 register 0x15 by writing a 0x1801. This should enable GPIO8 and associate it with event 0. I also enabled the event status at page 5 register 0x18 by writing a 0x3f. This should enable the event status.

I then create an event on GPIO 8 by driving a hardware signal into GPIO 8. I verify that the PHYTER chip sees the event by reading from page 6 register 0x1e (GPIO Monitor). I can see that GPIO 8 bit has changed from a 0 to a 1.

But when I read the event status register, page 4 register 0x1e, it always returns a 0. I have tried this with rising and falling edge configurations and single and multiple triggers.

What am I missing?

  • To help me get up to speed, it would be good for me to understand some baseline information.  I would like to start with some basics and then zero in on the specific issue with event configuration. 

    What functionality have you been able to confirm with the device?  For example, are you able to read the PTP_TDR and see the PTP Clock time incrementing as expected?  Are you able to generate triggers?  Are you able to timestamp packets? 

    What additional configuration has been performed for the device?  Are you using Phy Status Frames, for example? 

    Patrick

  • Hi Patrick,

    We have much of the chip working just fine. We can read from the PTP_TDR and read the time. We can generate triggers. We are time stamping packets and we are reading Phy Status Frames. In fact we have implemented the1588 V2 Slave Only protocol using this chip along with your TI DSP F335 processor. It is running on a network with an Endrun Grandmaster where we are able to get agreement to around 100ns.

    I can see the hardware event happening by reading the GPIO Monitor register. I can see that GPIO 8 changes states. However, I can not read the event status or the event  time.

    Thanks,

    Drew Tkac

  • Drew,

    How is the PHY Status Frame Configuration Register 0 (address 0x18 on page 5) configured?  If Events are enabled via PSF, they would be passed up via PSF instead of being returned via the Event Status Register.

    Patrick

  • I enabled the event status at page 5 register 0x18 by writing a 0x3f. This enables the events?

  • Drew,

    My mistake, I overlooked the fact that you had provided that register configuration previously.  Writing 0x1801 to the PTP Event Configuration Register (PTP_EVNT), address 0x15 on page 5, will enable the event.  No additional write is needed to enable event status. 

    Writing 0x3F to the PHY Status Frame Configuration Register 0 (PSF_CFG0), address 0x18 on page 5, will configure the device to provide the Event timestamp via a Phy Status Frame.  Could disable the Event Phy Status Frame enable by adjusting this write to 0x3E and see if the event is returned via the registers?

    Patrick

  • Hi Patrick,

    I just tried setting PSF_CFG1 to 0x1e and I did get one event after power up when I asserted the hardware signal. Yeaaa! However subsequent toggles of the hardware line going into GPIO 8 did not cause additional events. It sounds like I am not resetting or re-enabling something after the first event.

    Thanks,

    Drew

  • Hi Patrick,

    Disregard the previous post regarding additional events. I had the single event flag set in the PTP_EVNT register. I had forgotten that I set that when I was trying different configurations.

    So it all seems to work as expected. Thank you so much. I would have never figured that out logically. I may have blundered around to a solution. It seems counter intuitive to not enable the event flag to get the events. But it make sense now that I understand that your really enabling the event in the PSR only.

    Thanks for your help.

    Drew

  • Drew,

    Good news.  Just to close the loop could you post the final configuration values that you used for the PTP_EVNT register and the PSF_CFG0 register?  I believe the values might be:

    PTP_EVNT:  0x6801

    PSF_CFG0:  0x001E

    Is that correct?  This information may be useful to others who encounter similar issues.

    Thanks,

    Patrick

  • Sure thing Patrick,

    Setting are:

    ptSendPhy(0x5, 0x15, 0x4801);   // We are using leading edge, multiple trigger, GPIO 8, event 0 PTP_EVNT

    ptSendPhy(0x5, 0x18, 0x3e); // Enable all except event PTP_CFG0

    Thanks again for your help!

    Drew