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DS64BR401 Swap Input/Output Signals

Other Parts Discussed in Thread: DS64BR401

Hi,

We have obtained customer requests.
Is it not problem to swap the wiring by the convenience of the layout as follows(Proposal1, Proposal2)?
We swap the certain differential input/output channels.
Is there something affect on the performance?


(a) Proposal1
Input signals and output signals of Ch0 and Ch2 were connect normally,
Input signals of Ch1 and Ch3 are swapped(output signals are inverted in RX-IC).

TX-IC        DS64BR401         RX-IC
[Ch0]    Cs              Cs
TX0(+)----||--IB0(+)--OB0(+)---||---RX0(+)--|Differential to Single Converter
TX0(-)----||--IB0(-)--OB0(-)---||---RX0(-)--|

[Ch1]    Cs              Cs
TX1(+)----||--IB1(-)--OB1(-)---||---RX1(-)--|Differential to Single Converter + Inverter
TX1(-)----||--IB1(+)--OB1(+)---||---RX1(+)--|

[Ch2]    Cs              Cs
TX2(+)----||--IB2(+)--OB2(+)---||---RX2(+)--|Differential to Single Converter
TX2(-)----||--IB2(-)--OB2(-)---||---RX2(-)--|

[Ch3]    Cs              Cs
TX3(+)----||--IB3(-)--OB3(-)---||---RX3(-)--|Differential to Single Converter + Inverter
TX3(-)----||--IB3(+)--OB3(+)---||---RX3(+)--|


(b) Proposal2
Input signals and output signals of Ch0 and Ch2 were connect normally,
Input signals and internal singals of Ch1 and Ch3 are swapped.

TX-IC        DS64BR401         RX-IC
[Ch0]    Cs              Cs
TX0(+)----||--IB0(+)--OB0(+)---||---RX0(+)--|Differential to Single Converter
TX0(-)----||--IB0(-)--OB0(-)---||---RX0(-)--|

[Ch1]    Cs              Cs
TX1(+)----||--IB1(-)--OB1(+)---||---RX1(+)--|Differential to Single Converter
TX1(-)----||--IB1(+)--OB1(-)---||---RX1(-)--|

[Ch2]    Cs              Cs
TX2(+)----||--IB2(+)--OB2(+)---||---RX2(+)--|Differential to Single Converter
TX2(-)----||--IB2(-)--OB2(-)---||---RX2(-)--|

[Ch3]    Cs              Cs
TX3(+)----||--IB3(-)--OB3(+)---||---RX3(+)--|Differential to Single Converter
TX3(-)----||--IB3(+)--OB3(-)---||---RX3(-)--|


We think that our proposal1 is not problem, but the proposal2 is problem.
Please tell us about it.


Best Regards,
Kato

  • Kato-San,

    I think both proposals should work. In proposal 1 there is a need for inverter however i don't know what is the data rate in this application. At high data rates finding a low cost inverter could be difficult. I think proposal 2 would be preferred. It is my understanding they are doing this to simplify their PCB layout ? As long as the signal is electrically compatible with the input and they are differential signal the device does not know whether one side is positive or negative.

    Regards,,nasser 

  • Hi, Nasser-san,

    Thank you for your information.
    We have a question about the proposal2, understand that this is not a problem for logical signal.
    If the delays(or TR/TF) of input differential signals is differential between TX*(+) and TX*(-),
    Does timing deviation occur between channel0(or channel2) and channel1(or channel3) by swap of the internal signals?
    We think that the phase relationship is to be reversed between RX1(+) and RX1(-) by delay mismatch of input differential signals.
    There is not a problem about the proposal1.
    How do you think about it?

    Best Regards,
    Kato

  • Hi Kato-San,

    I believe you are refering to the skew when you talk about delay in Tr/Tf of the input differential signals. My understanding is that the traces on the input differential signals are matched so there is no skew or delay between Tr/Tf. In any case, the traces have to be matched on the PCB. So as far as  i can say, proposal 2 should work as long as traces are matched(i.e the same length).

    Regards,,nasser

  • Hi, Nasser-san,

    Thank you for your information.
    We understood that there is no problem about both of proposals.
    We can reply to our customers with confidence.
    Thank you so much.

    Best Regards,
    Kato