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TFP410 problem

Omri16467
Prodigy 30 points
Other Parts Discussed in Thread: TFP410

hi all,

I use The TFP410 Transmitter in my new board...

I tried to display something like white screen via the DVI-D connector but nothing was display..

i tested the I2C port and its work fine although i dont use it..

the timing with the HSYNC, VSYNC and DE signals are match with the DVI and VGA specs and I still cant get the screen works..

can anyone help me?

  • 0
    TI__Genius 11400 points

    Omri,

    Can you provide schematics of the TFP410 section? (You can post here or email to ufields@ti.com). 

    Can you also tell me what resolution and refresh rate you are using?  Do lower resolutions have the same problem (640 x 480)?

  • 0 in reply to Undrea Fields
    TI__Genius 16440 points

    E-mail thread continued on this subject:

    A great help would be to actually capture the inputs to the TFP410 to verify the timing.  DE, HSYNC and VSYNC and input clock to verify clock rate.  Can you also use a differential probe to probe the Tx outputs and verify that data is transmitting?

    Also, do you have access to the outputs of the receiver end? 

     Regards,

    Undrea

    Sent: Sunday, November 15, 2009 2:01 AM
    To: Fields, Undrea
    Subject: Re: TFP410 problem

    hey Undrea,

    I tried to use resolution of 640*480 and the screen still shows "no signal"

    DKEN is kept low..

    whats else it can be?

    thank you for your replay.

    Omri.

    On Wed, Nov 11, 2009 at 5:50 PM, Fields, Undrea wrote:

    Omri,

    Also, the DKEN pin is normally kept low, or if DKEN is high, then DK[3:1] pins are normally kept low.

    Regards,

    Undrea

    From: omri cohen [mailto:omriko.87@gmail.com]
    Sent: Wednesday, November 11, 2009 3:46 AM
    To: Fields, Undrea
    Subject: Re: TFP410 problem

    Hi Undrea,

    The state of the pins:

    Pin 13 ISEL/#RST = Low

    Pin 35 DKEN = High
    Pin 6 CTL3/DK3 = High
    Pin 7 CTL2/DK2 = High
    Pin 8 CTL1/DK1 = High

    I use 800*600 resolution.. and I'm sure that the timing of HSYNC and VSYNC are currect. I use that signals with VGA and its

    work fines. The DE signal I generate according to the DVI Specification (http://www.ddwg.org/lib/dvi_10.pdf).

    The CLK signal (only CLK+ is used) is generate according to the Datasheet.

    I tried to probe the TXC- and TXC+ pins but I get nothing... just some noises.

    I will try some other resolution even though I dont think thats the problem.

    thank you for your answer

    Omri.


    On Tue, Nov 10, 2009 at 5:44 PM, Fields, Undrea wrote:

    Hi Omri,

    Can you tell me what the state is of the following pins:
    Pin 13 ISEL/RST#
    Pin 35 DKEN
    Pin 6 CTL3/DK3
    Pin 7 CTL2/DK2
    Pin 8 CTL1/DK1

    Also, a couple additional questions:
    What resolution is being used?
    If the resolution is changed is there anything displayed (640 x 480)?
    Has the timing out of the FPGA been verified (CLK, HSYNC, VSYNC and DE)?  Is it possible to send any timing captures into the transmitter?
    Is there anyway to probe a few signals on the output of the receiver to see if data is actually being received?

    Regards,
    Undrea
    -----Original Message-----
    From: omri cohen [mailto:omriko.87@gmail.com]
    Sent: Sunday, November 08, 2009 3:59 AM
    To: Fields, Undrea
    Subject: TFP410 problem

    hi Undrea,
    I'm Omri from TI E2E forum with the TFP410's problem..

    here's the schematic of the TFP410

    there are some changes in the schematic:
    - Pin 9 (EDGE) is short to the DVcc 3.3
    - U24 is a double connector(DVI+VGA) and in theDVI connector, pin 14
    short to the Vcc 5v , and pin 15 short to GND

    i hope youll fine my mistake
    Thank you very much!