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LMH0340 - LVDS input at device power down

Kawai
Guru 19785 points
Other Parts Discussed in Thread: LMH0340

Hi, Team,

Our customer is using LMH0340. They will power down the device when system is not using LMH0340.
But, in the customer application, there would be a case of LVDS signal input when device powered down.
In this condition, customer monitored 0.7V at VDD pin.(Maybe through the ESD diode to VDD pin)

If you see the absolute maximum ratings, it is inside the specification, but is it OK use in such condition ? Would there be any problem such as latch up ?

Best Regards,
Kawai

  • 0
    TI__Guru* 93670 points

    Kawai-San,

    Can you please ask the customer to measure the current consumption by the LVDS input pin? If it is less than 3-4mA then we think this should be ok. This tells us the driver is limiting the current. Otherwise if it is in 20mA range there could be long term damage.

    Regards,,nasser 

  • 0 in reply to Nasser Mohammadi
    Guru 19785 points

    Nasser-san,

    I understood  that if the LVDS driver's (such as the FPGA) driving current is limited to the value of 3-4mA, LVDS signal could be input to the powered down LMH0340.

    What if the current was 5mA, 10mA, or 15mA ?

    We will ask customer for measurement.

    ---

    I am also still asking customer to disable LVDS before LMH0340 power down, if possible.

    Best Regards,

    Kawai

  • 0 in reply to Kawai
    TI__Guru* 93670 points

    Hi Kawai-San,

    I think in the long term 5,10, or 15mA could potentially damage the device and it is not advised to operate the device in this mode. Please note we have not characterized the device under this condition.

    Regards,,nasser