Do you have a schematic about DP83849I connected to AM3358.

Wayne,

I am not aware of a reference design using the AM3358 + DP83849I, but I can address your remaining questions. 

To provide robust timing for RMII, we want the DP83849 and the MAC to have the same clock with a minimum of skew.  The skew associated with the buffer inside the DP83849 may be enough to marginalize the RMII timing. I would recommend against using CLK2MAC as the clock source for the two AM3358 inputs.

The EVM schematic is available at:

http://www.ti.com/lit/snlr002

Patrick

AM3358 has two MAC clock pins. RMII1_REF_CLK and RMII2_REF_CLK. these two pins need to get clock signal from PHY.  should CLK2MAC be connected to  RMII1_REF_CLK and RMII2_REF_CLK together? Is there impedance matching risk? 

Wayne,

The CLK2MAC pin should not be connected to either RMII REF_CLK input.  The issue is not related to impedance matching but interface timing, as noted in the previous post.  Although there are implementations that do allow connecting a Phy clock output to the MAC, technically this is outside the RMII specification.  The RMII specification states that:

A single clock reference is sourced from the MAC to PHY (or from an external source).

What is the clock source for the DP83849?  Is it a 50MHz oscillator or a clock from another source?  I would suggest buffering this signal to create a small clock tree that can supply all three sources (Phy reference clock plus both RMII reference clocks).

Patrick

Thanks for your replay. 

Now, Customer has two 50MHz clock source  from a buffer chip. what's your suggestions for this application.

If customer want to use a 50MHz oscillator to supply clock signal for DP83849. what's your suggestion?

Wayne,

Is there more information required or can this thread be closed?

Patrick