I have a new design with a Freescale P2041 connected to the XIO2001. The XIO2001 is not being enumerated by the processor. I am using a 100MHz LVDS differential clock buffer in the system and did not carefully check the clock specs of the XIO2001. I now see that the XIO2001 wants an HCSL clock. Before I spin the board and add an HCSL clock I want verify that this is the issue. I have modified LVDS clock by insering a series cap and a 50 ohm termination (on the XIO2001 side of cap) to each of the differential clock lines. I measured the modified clock differentially with a scope and now see a 750mvpp centered at 0V. I am still not enumeration.
I believe the link routing is good becasue we followed the routing guides and I also have two other PCIe devices/chips in the system (an FPGA and a Video chip) that are both enumeration consistantly to the P2014.
My general questions are
Should the clock mod work?
Are there any known issue connecting to the P2041? Are there any desired link settings I should be changing in the P2041?
Are there any troubleshooting steps I can use to help pin point the problem?
Thanks
Frank Porfido
