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LMH0340 TXCLK AC timing

Kikuo Mita
Intellectual 2515 points
Other Parts Discussed in Thread: LMH0340

Hi Team,

Please advise me on LMH0340 TXCLK AC parameter.
The datasheet (page 6) insists that the minimum transition time of TXCLK input is 0.5ns.

tCIT TxCLKIN   Transition Time   See Figure 3     0.5    1.0    3.0   ns

Isn’t it typo?
Because almost all LVDS devices does not meet this minimum specification.
Compering the half clock period of DDR (600 MHz = 3.3ns), the transition time
eats timing margin.

Please check if it is true or not.
If it is true, please provide reference circuit for interfacing major LVDS driver
to meet this specifications.

Mita

  • 0
    TI__Genius 13475 points

    Mita-san

    When we characterized the LMH0340 we did so with transition times on the clock of from 0.5ns to 3ns - the Cyclone III has a typical transition time of 500ps with a 5pf load, but we found that on our typical PCBs, there was more than 5pF of capacitance between the LMH0340 input and the PCB parasitics, and as a result, we never saw faster than 500ps from any Part - I don't remember Xilinx specifying their rise/fall times, but their I/O tended to be a bit slower than the Altera I/O.

    If you have a faster transition time, my only real concern would be with transmission line effects leading to ringing on the TXCLK input - so long as that is kept under control, I wouldn't worry about TXCLK transitions being too fast.

    Mark

     

  • 0 in reply to Mark Sauerwald88474
    TI__Intellectual 2515 points

    Mark-san,

    Thank you for the answr.

    Mita