ISO3088 RS-485 Transceiver - 3.3V Logic Interface, LOW level at 2.8V instead of GND

Hi Luis,

Some screen shots and a schematic would definitely help, but let me first give some input with what you have given me so far,

The 3.3V for VCC1 and 5.0 for VCC2 are good.

I noticed that on the logic side the voltage level (on pin "R") for a "0" (LOW level) is somewhere around 2.8V instead of GND. I went into the lab and tested a device I had, and to make the output sit at 2.8 volts, I needed to pull the R pin to VCC1 (3.3 volts) with an 8 ohm resitor. With a load this load the output is sinking 50mA+ of current.

I don't think a digital FPGA input is considered a serious load on the "R" pin and there are no pull-x resistors. I would agree, the input should be high impedance and therefore not load the pin. But the issue you are seeing makes me think the pin is trying to drive it low, but is unable. Can you check my measuring the input impedance of the FPGA pin? Could the pin possibly be in an ouput state and fighting the falling edge?

The RS-485 bus side is rock solid and works great with different transceivers/ bus drivers. Cable length is really short too and bus lines are terminated. Good.

The Logic Side voltage supply and ground are provided from the FPGA board and the 3.3Vs are verified to be absolutely stable. I also tested connection to GND of the FPGA board on all three GND pins.  I am glad you checked that all 3 grounds on both sides of the device are connected, because they are not always neccasarily connected internally. I do not know if they are on this device and would have to check with design.

The 5V bus side voltage supply and ground are provided from a different power supply. => Proper isolation between Logic Side and Bus Side. Sounds fine. Even if the grounds were tied together, we should still be able to have communication.

If you could send some screen shots of the bus voltages with the D and R pins. Also please verify the voltages of the DE and RE pins.

Thanks,

John

Hi John,

First of all: Thanks so much for your input and trip to the lab!! I really appreciate it.

I wanted to let you know that I might have found the root cause for those 2.8V "LOW" levels:

Crosstalk.

I think that what I saw on the scope was a signal received by a different transceiver IC on the board (let's call him IC2).

The wicked signal on the "R" pin of IC1 was probably crosstalked over from the line:

"R" pin of IC2 ---> FPGA_INPUT_FOR_IC2.

The logic levels on IC2 are of course just fine! (HIGH=3.3V; LOW=GND)

I'm still working on the system but wanted to give you a quick heads up.

From where I stand now, the transceiver ICs work as expected.

Thank you for your great input and testing. It really helped.

Have a great week.

Best Regards

Luis