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Deserializer for multidrop STP Cable ~1Gbit/s (DS92LV2412 possible?)

Other Parts Discussed in Thread: DS92LV2412, DS32ELX0421, DS32ELX0124, DS30EA101, DS100MB201

Hi,
Is there any deserializers that can be used in a multidrop configuration ?

Configuration:
Data source (FPGA) ~800Mbit-1300Mbit/s
The same signal will be broadcasted/distributed to up to 16 drop points over
a STP cable. Total length of the cable(s) will be up to 15 meters.

Would it be possible to use for example DS92LV2412 in a multidrop configuration ?
Do I need signal conditioning between each drop point ?

Kind regards
Tobias






  • Tobias

    A couple of thoughts:

    The DS32ELX0421 serializer could be connected to your FPGA, and the serialized output would be received by the DS32ELX0124 - there are a couple of things that might make this chipset interesting in your application:  The serializer provides you with two outputs - a primary and a redundant, allowing you to start off two different strings.  The Receiver has a retimed loopthrough output which will enable you to daisy chain a large number of these links.   The chipset will support data rates of up to ~3Gbps.   With no additional signal conditioning you can expect  to meet your 15m requirement, or the length can be extended with a cable equalizer such as the DS30EA101.

    Another possibility would be to use the A part like the DS92LV2412.  These parts are more self contained SerDes devices, requiring less support from your FPGA, but they are not able to support as high of a datarate, nor as many links.    If I were to use this sort of device, I think that I would use a device like the DS100MB201 mux buffer at each receiver - this would allow you to receive the signal, and generate a new signal to go on to the next deserializer, as well as have one to use locally.  Since there is no reclocking, the number of hops will be more limited than if you use a part like the DS32ELX0421.

     

    Mark Sauerwald

     

  • Hi Mark,
    Thanks for your answer. The DS32ELX0124 looks very interesting because of the reclocked output. As I understand it, there is no real limit from how many segments I can build? I suppose reclocked "loopthrough" is what I need in my application.

    Added question: Can I run this link on a 12 inch line on a FR4 pcb without problem ?

    However there is no FPGA at the receivers, and the maximum speed I can handle behind the receiving Point is 120Mbit/s (per channel).
    Is 125MHz the absolute low limit for the 0124 ? (Is there a CPLD with LVDS ports maybe I could use as glue ??)
    Any other deserializer with reclocked output ?


    Tobias