DP83348i : RX_CLK to RXD[3:0], RX_DV, RX_ER Delay

MONZAIN Baptiste

Hello,

I just have a question about the parameter T2.5.2 of the datasheet (RX_CLK to RXD[3:0], RX_DV, RX_ER Delay). This delay is specified between 10ns and 30ns. Our processor has a setup time (RXD[3:0], RX_DV, RX_ER setup time to RX_CLK) of 10ns minimum. 10ns + 30ns = 40ns, whitch is the periode of the clock : we have no marging. So I would like to know what creates such a dispersion (10ns-30ns) on the T2.5.2 parameter, in order to understand our risks. Is it operating temperature ? is it manufacturing of the die ? other thing ? Thank you for your answer.

Best regards.

Baptiste Monzain

over 12 years ago

0 Patrick OFarrell over 12 years ago

TI__Mastermind 31600 points

The timing shown in the datasheet reflects the timing described in the IEEE 802.3 specification. The intent of the timing in the datasheet is to indicate that the device conforms to the IEEE specification. If your processor is compliant with the IEEE specification, there should be no issues.

Patrick

0 MONZAIN Baptiste over 12 years ago in reply to Patrick OFarrell

Prodigy 70 points

Hello Patrick, and thank you for your answer. Our rocessor supports IEEE 802.3 standard. But the marging seems short for us. Please could you provide information about the risk to have T2.5.2 near 30ns, and what are the parameters that could impact it ?

Thank you in advance,

Baptiste.

0 MONZAIN Baptiste over 12 years ago in reply to MONZAIN Baptiste

Prodigy 70 points

Dear Patrick, any news about this question ?

0 Patrick OFarrell over 12 years ago in reply to MONZAIN Baptiste

TI__Mastermind 31600 points

The device is designed to meet this specification with 4-6ns of margin over all conditions (temperature, voltage, device variation, etc.). If your processor is compliant with the IEEE specification, there should be no issues.

Patrick

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DP83348i : RX_CLK to RXD[3:0], RX_DV, RX_ER Delay