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TLK 6002 - PLL does not lock

Horia Naidin
Prodigy 30 points
Other Parts Discussed in Thread: TLK6002

Hello, 

I'm trying to deserialize a 1.25Gbps signal with TLK6002. The problem is that the PLL does not lock, all the channel status registers remaining at 0. Input high-speed signal and REFCLK are properly provided. 

The rest of the non-default registers: 

Register 0x00 = 0600

Register 0x01 = 01AD

Register 0x03 = 1900

Register 0x04 = 0000

Register 0x05 = 0000

Register 0x06 = C000

Register 0x07 = 0708

Register 0x08 = 3D7C 

What could be the problem?

Thank you in advance

  • 0
    TI__Guru* 81035 points

    Hi Horia,

    I just want to verify, the REFCLK is provided to the REFCLK0P and REFCLK0N pins at 125MHz and meets the conditions of Table 4.4 of the datasheet? I believe these register settings should be okay.

    Best regards,

    Matt

  • 0 in reply to Matt Sunna
    Prodigy 30 points

    Hi Matt,

    As per your suggestion, I checked the REFCLK and it turned out it had a wrong voltage level. Now I've fixed it with an external oscillator, but still get nothing register wise - same results as before.

    Is it possible that a voltage level of ~2.5V has distroyed the pin? 

    Regards

    Horia

  • 0 in reply to Horia Naidin
    Prodigy 30 points

    Hello,

    I've also uploaded a few oscilloscope screenshots to illustrate the nature of my problem:

    Reference clock

    1.8V Power supply

    1.0V Power supply

    MDIO Communication (reading register 0x01)

    I would also like to know whether there is a way to see what causes the PLL not to lock (the input signal doesn't have the right amplitude, reference clock is not accurate enough with respect to incoming data rate, etc).


    Thank you in advance


  • 0 in reply to Horia Naidin
    TI__Guru* 81035 points

    Hi Horia,

    I suggest checking a few things:

    - Are you able to read back other MDIO registers successfully with the expected values? I just want to verify the MDIO interface is not reporting all zeros.

    - Try to increase the amplitude of the reference clock to see if it makes any difference. The differential input voltage range is 250mV to 2000mV.

    - From your register settings, REFCLK_0 is selected. Is your clock source connected to the correct REFCLK input?

    - Make sure your REFCLK is synchronous to the TXCLK_A/B input.

    - Also, try to changing the REFCLK frequency to different values if possible with a signal generator. If a different frequency is able to lock the PLL, then something may be wrong with the rate settings.

    - Is the clock coming from a clean, low jitter source?

    Best regards,

    Matt