On the SN65LVDS31 LVDS driver, is it OK to connect the input without a pullup or pulldown?
I assume it’s a CMOS input stage and since this input is sourced from our FPGA, there will be a short duration when the input will float while board/FPGA is powering up. I just wanted to make sure there wouldn’t be a situation where the input oscillates or draws high current during power
